1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=arm-eabi -mattr=+armv8.2-a,+fullfp16,+neon -float-abi=hard < %s | FileCheck %s --check-prefix=CHECKHARD
3; RUN: llc -mtriple=arm-eabi -mattr=+armv8.2-a,+fullfp16,+neon -float-abi=soft < %s | FileCheck %s --check-prefix=CHECKSOFT
4
5define float @test_vget_lane_f16_1(<4 x half> %a) nounwind {
6; CHECKHARD-LABEL: test_vget_lane_f16_1:
7; CHECKHARD:       @ %bb.0: @ %entry
8; CHECKHARD-NEXT:    vcvtt.f32.f16 s0, s0
9; CHECKHARD-NEXT:    bx lr
10;
11; CHECKSOFT-LABEL: test_vget_lane_f16_1:
12; CHECKSOFT:       @ %bb.0: @ %entry
13; CHECKSOFT-NEXT:    vmov d0, r0, r1
14; CHECKSOFT-NEXT:    vcvtt.f32.f16 s0, s0
15; CHECKSOFT-NEXT:    vmov r0, s0
16; CHECKSOFT-NEXT:    bx lr
17entry:
18  %elt = extractelement <4 x half> %a, i32 1
19  %conv = fpext half %elt to float
20  ret float %conv
21}
22
23define float @test_vget_lane_f16_2(<4 x half> %a) nounwind {
24; CHECKHARD-LABEL: test_vget_lane_f16_2:
25; CHECKHARD:       @ %bb.0: @ %entry
26; CHECKHARD-NEXT:    vcvtb.f32.f16 s0, s1
27; CHECKHARD-NEXT:    bx lr
28;
29; CHECKSOFT-LABEL: test_vget_lane_f16_2:
30; CHECKSOFT:       @ %bb.0: @ %entry
31; CHECKSOFT-NEXT:    vmov d0, r0, r1
32; CHECKSOFT-NEXT:    vcvtb.f32.f16 s0, s1
33; CHECKSOFT-NEXT:    vmov r0, s0
34; CHECKSOFT-NEXT:    bx lr
35entry:
36  %elt = extractelement <4 x half> %a, i32 2
37  %conv = fpext half %elt to float
38  ret float %conv
39}
40
41define float @test_vget_laneq_f16_6(<8 x half> %a) nounwind {
42; CHECKHARD-LABEL: test_vget_laneq_f16_6:
43; CHECKHARD:       @ %bb.0: @ %entry
44; CHECKHARD-NEXT:    vcvtb.f32.f16 s0, s3
45; CHECKHARD-NEXT:    bx lr
46;
47; CHECKSOFT-LABEL: test_vget_laneq_f16_6:
48; CHECKSOFT:       @ %bb.0: @ %entry
49; CHECKSOFT-NEXT:    vmov d1, r2, r3
50; CHECKSOFT-NEXT:    vcvtb.f32.f16 s0, s3
51; CHECKSOFT-NEXT:    vmov r0, s0
52; CHECKSOFT-NEXT:    bx lr
53entry:
54  %elt = extractelement <8 x half> %a, i32 6
55  %conv = fpext half %elt to float
56  ret float %conv
57}
58
59define float @test_vget_laneq_f16_7(<8 x half> %a) nounwind {
60; CHECKHARD-LABEL: test_vget_laneq_f16_7:
61; CHECKHARD:       @ %bb.0: @ %entry
62; CHECKHARD-NEXT:    vcvtt.f32.f16 s0, s3
63; CHECKHARD-NEXT:    bx lr
64;
65; CHECKSOFT-LABEL: test_vget_laneq_f16_7:
66; CHECKSOFT:       @ %bb.0: @ %entry
67; CHECKSOFT-NEXT:    vmov d1, r2, r3
68; CHECKSOFT-NEXT:    vcvtt.f32.f16 s0, s3
69; CHECKSOFT-NEXT:    vmov r0, s0
70; CHECKSOFT-NEXT:    bx lr
71entry:
72  %elt = extractelement <8 x half> %a, i32 7
73  %conv = fpext half %elt to float
74  ret float %conv
75}
76
77define <4 x half> @test_vset_lane_f16(<4 x half> %a, float %fb) nounwind {
78; CHECKHARD-LABEL: test_vset_lane_f16:
79; CHECKHARD:       @ %bb.0: @ %entry
80; CHECKHARD-NEXT:    vcvtt.f16.f32 s1, s2
81; CHECKHARD-NEXT:    bx lr
82;
83; CHECKSOFT-LABEL: test_vset_lane_f16:
84; CHECKSOFT:       @ %bb.0: @ %entry
85; CHECKSOFT-NEXT:    vmov d0, r0, r1
86; CHECKSOFT-NEXT:    vmov s2, r2
87; CHECKSOFT-NEXT:    vcvtt.f16.f32 s1, s2
88; CHECKSOFT-NEXT:    vmov r0, r1, d0
89; CHECKSOFT-NEXT:    bx lr
90entry:
91  %b = fptrunc float %fb to half
92  %x = insertelement <4 x half> %a, half %b, i32 3
93  ret <4 x half> %x
94}
95
96define <8 x half> @test_vset_laneq_f16_1(<8 x half> %a, float %fb) nounwind {
97; CHECKHARD-LABEL: test_vset_laneq_f16_1:
98; CHECKHARD:       @ %bb.0: @ %entry
99; CHECKHARD-NEXT:    vcvtt.f16.f32 s0, s4
100; CHECKHARD-NEXT:    bx lr
101;
102; CHECKSOFT-LABEL: test_vset_laneq_f16_1:
103; CHECKSOFT:       @ %bb.0: @ %entry
104; CHECKSOFT-NEXT:    vmov d1, r2, r3
105; CHECKSOFT-NEXT:    vldr s4, [sp]
106; CHECKSOFT-NEXT:    vmov d0, r0, r1
107; CHECKSOFT-NEXT:    vcvtt.f16.f32 s0, s4
108; CHECKSOFT-NEXT:    vmov r2, r3, d1
109; CHECKSOFT-NEXT:    vmov r0, r1, d0
110; CHECKSOFT-NEXT:    bx lr
111entry:
112  %b = fptrunc float %fb to half
113  %x = insertelement <8 x half> %a, half %b, i32 1
114  ret <8 x half> %x
115}
116
117define <8 x half> @test_vset_laneq_f16_7(<8 x half> %a, float %fb) nounwind {
118; CHECKHARD-LABEL: test_vset_laneq_f16_7:
119; CHECKHARD:       @ %bb.0: @ %entry
120; CHECKHARD-NEXT:    vcvtt.f16.f32 s3, s4
121; CHECKHARD-NEXT:    bx lr
122;
123; CHECKSOFT-LABEL: test_vset_laneq_f16_7:
124; CHECKSOFT:       @ %bb.0: @ %entry
125; CHECKSOFT-NEXT:    vmov d1, r2, r3
126; CHECKSOFT-NEXT:    vldr s4, [sp]
127; CHECKSOFT-NEXT:    vmov d0, r0, r1
128; CHECKSOFT-NEXT:    vcvtt.f16.f32 s3, s4
129; CHECKSOFT-NEXT:    vmov r0, r1, d0
130; CHECKSOFT-NEXT:    vmov r2, r3, d1
131; CHECKSOFT-NEXT:    bx lr
132entry:
133  %b = fptrunc float %fb to half
134  %x = insertelement <8 x half> %a, half %b, i32 7
135  ret <8 x half> %x
136}
137