1; RUN: llc -mtriple=arm-eabi -mattr=+armv8.2-a,+fullfp16,+neon -float-abi=hard -O1 < %s | FileCheck %s
2; RUN: llc -mtriple=arm-eabi -mattr=+armv8.2-a,+fullfp16,+neon -float-abi=soft -O1 < %s | FileCheck %s
3
4define <4 x half> @vld1d_lane_f16(half* %pa, <4 x half> %v4) nounwind {
5; CHECK-LABEL: vld1d_lane_f16:
6; CHECK: vld1.16 {d{{[0-9]+}}[3]}, [r0:16]
7entry:
8  %a = load half, half* %pa
9  %res = insertelement <4 x half> %v4, half %a, i32 3
10  ret <4 x half> %res
11}
12
13define <8 x half> @vld1q_lane_f16_1(half* %pa, <8 x half> %v8) nounwind {
14; CHECK-LABEL: vld1q_lane_f16_1:
15; CHECK: vld1.16 {d{{[0-9]+}}[1]}, [r0:16]
16entry:
17  %a = load half, half* %pa
18  %res = insertelement <8 x half> %v8, half %a, i32 1
19  ret <8 x half> %res
20}
21
22define <8 x half> @vld1q_lane_f16_7(half* %pa, <8 x half> %v8) nounwind {
23; CHECK-LABEL: vld1q_lane_f16_7:
24; CHECK: vld1.16 {d{{[0-9]+}}[3]}, [r0:16]
25entry:
26  %a = load half, half* %pa
27  %res = insertelement <8 x half> %v8, half %a, i32 7
28  ret <8 x half> %res
29}
30
31define void @vst1d_lane_f16(half* %pa, <4 x half> %v4) nounwind {
32; CHECK-LABEL: vst1d_lane_f16:
33; CHECK: vst1.16 {d{{[0-9]+}}[3]}, [r0:16]
34entry:
35  %a = extractelement <4 x half> %v4, i32 3
36  store half %a, half* %pa
37  ret void
38}
39
40define void @vst1q_lane_f16_7(half* %pa, <8 x half> %v8) nounwind {
41; CHECK-LABEL: vst1q_lane_f16_7:
42; CHECK: vst1.16 {d{{[0-9]+}}[3]}, [r0:16]
43entry:
44  %a = extractelement <8 x half> %v8, i32 7
45  store half %a, half* %pa
46  ret void
47}
48
49define void @vst1q_lane_f16_1(half* %pa, <8 x half> %v8) nounwind {
50; CHECK-LABEL: vst1q_lane_f16_1:
51; CHECK: vst1.16 {d{{[0-9]+}}[1]}, [r0:16]
52entry:
53  %a = extractelement <8 x half> %v8, i32 1
54  store half %a, half* %pa
55  ret void
56}
57