1# RUN: llc -o /dev/null %s -mtriple=arm-eabi -mcpu=swift -run-pass  machine-scheduler  -enable-misched -verify-misched \
2# RUN:  -debug-only=machine-scheduler 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK_SWIFT
3# RUN: llc -o /dev/null %s -mtriple=arm-eabi -mcpu=cortex-a9 -run-pass  machine-scheduler  -enable-misched -verify-misched \
4# RUN:  -debug-only=machine-scheduler 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK_A9
5# RUN: llc -o /dev/null %s -mtriple=arm-eabi -mcpu=cortex-r52 -run-pass  machine-scheduler  -enable-misched -verify-misched \
6# RUN:  -debug-only=machine-scheduler 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK_R52
7# REQUIRES: asserts
8--- |
9  ; ModuleID = 'foo.ll'
10  source_filename = "foo.ll"
11  target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
12  target triple = "arm---eabi"
13
14  define i64 @foo(i16 signext %a, i16 signext %b)  {
15  entry:
16    %d = mul nsw i16 %a, %a
17    %e = mul nsw i16 %b, %b
18    %f = add nuw nsw i16 %e, %d
19    %c = zext i16 %f to i32
20    %mul8 = mul nsw i32 %c, %c
21    %mul9 = mul nsw i32 %mul8, %mul8
22    %add10 = add nuw nsw i32 %mul9, %mul8
23    %conv1130 = zext i32 %add10 to i64
24    %mul12 = mul nuw nsw i64 %conv1130, %conv1130
25    %mul13 = mul nsw i64 %mul12, %mul12
26    %add14 = add nuw nsw i64 %mul13, %mul12
27    ret i64 %add14
28  }
29
30# CHECK:       ********** MI Scheduling **********
31# CHECK:       SU(2):   %2:gpr = SMULBB %1:gpr, %1:gpr, 14, $noreg
32# CHECK_A9:    Latency    : 2
33# CHECK_SWIFT: Latency    : 4
34# CHECK_R52:   Latency    : 4
35#
36# CHECK:       SU(3):   %3:gprnopc = SMLABB %0:gprnopc, %0:gprnopc, %2:gpr, 14, $noreg
37# CHECK_A9:    Latency    : 2
38# CHECK_SWIFT: Latency    : 4
39# CHECK_R52:   Latency    : 4
40#
41# CHECK:       SU(4):   %4:gprnopc = UXTH %3:gprnopc, 0, 14, $noreg
42# CHECK_A9:    Latency    : 1
43# CHECK_SWIFT: Latency    : 1
44# CHECK_R52:   Latency    : 3
45#
46# CHECK:       SU(5):   %5:gprnopc = MUL %4:gprnopc, %4:gprnopc, 14, $noreg, $noreg
47# CHECK_A9:    Latency    : 2
48# CHECK_SWIFT: Latency    : 4
49# CHECK_R52:   Latency    : 4
50#
51# CHECK:       SU(6):   %6:gprnopc = MLA %5:gprnopc, %5:gprnopc, %5:gprnopc, 14, $noreg, $noreg
52# CHECK_A9:    Latency    : 2
53# CHECK_SWIFT: Latency    : 4
54# CHECK_R52:   Latency    : 4
55#
56# CHECK:       SU(7):   %7:gprnopc, %8:gprnopc = UMULL %6:gprnopc, %6:gprnopc, 14, $noreg, $noreg
57# CHECK_A9:    Latency    : 3
58# CHECK_SWIFT: Latency    : 5
59# CHECK_R52:   Latency    : 4
60#
61# CHECK:       SU(11):   %13:gpr, %14:gprnopc = UMLAL %6:gprnopc, %6:gprnopc, %13:gpr(tied-def 0), %14:gprnopc(tied-def 1), 14, $noreg, $noreg
62# CHECK_SWIFT: Latency    : 7
63# CHECK_A9:    Latency    : 3
64# CHECK_R52:   Latency    : 4
65# CHECK:  ** ScheduleDAGMILive::schedule picking next node
66...
67---
68name:            foo
69alignment:       4
70exposesReturnsTwice: false
71legalized:       false
72regBankSelected: false
73selected:        false
74tracksRegLiveness: true
75registers:
76  - { id: 0, class: gprnopc }
77  - { id: 1, class: gpr }
78  - { id: 2, class: gpr }
79  - { id: 3, class: gprnopc }
80  - { id: 4, class: gprnopc }
81  - { id: 5, class: gprnopc }
82  - { id: 6, class: gprnopc }
83  - { id: 7, class: gprnopc }
84  - { id: 8, class: gprnopc }
85  - { id: 9, class: gpr }
86  - { id: 10, class: gprnopc }
87  - { id: 11, class: gprnopc }
88  - { id: 12, class: gprnopc }
89  - { id: 13, class: gpr }
90  - { id: 14, class: gprnopc }
91liveins:
92  - { reg: '$r0', virtual-reg: '%0' }
93  - { reg: '$r1', virtual-reg: '%1' }
94frameInfo:
95  isFrameAddressTaken: false
96  isReturnAddressTaken: false
97  hasStackMap:     false
98  hasPatchPoint:   false
99  stackSize:       0
100  offsetAdjustment: 0
101  maxAlignment:    0
102  adjustsStack:    false
103  hasCalls:        false
104  maxCallFrameSize: 0
105  hasOpaqueSPAdjustment: false
106  hasVAStart:      false
107  hasMustTailInVarArgFunc: false
108body:             |
109  bb.0.entry:
110    liveins: $r0, $r1
111
112    %1 = COPY $r1
113    %0 = COPY $r0
114    %2 = SMULBB %1, %1, 14, $noreg
115    %3 = SMLABB %0, %0, %2, 14, $noreg
116    %4 = UXTH %3, 0, 14, $noreg
117    %5 = MUL %4, %4, 14, $noreg, $noreg
118    %6 = MLA %5, %5, %5, 14, $noreg, $noreg
119    %7, %8 = UMULL %6, %6, 14, $noreg, $noreg
120    %13, %10 = UMULL %7, %7, 14, $noreg, $noreg
121    %11 = MLA %7, %8, %10, 14, $noreg, $noreg
122    %14 = MLA %7, %8, %11, 14, $noreg, $noreg
123    %13, %14 = UMLAL %6, %6, %13, %14, 14, $noreg, $noreg
124    $r0 = COPY %13
125    $r1 = COPY %14
126    BX_RET 14, $noreg, implicit $r0, implicit $r1
127
128...
129