1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s --check-prefix=ARM
3; RUN: llc -mtriple=thumbv6t2-eabi %s -o - | FileCheck %s --check-prefix=THUMB2
4; RUN: llc -mtriple=thumb-eabi %s -o - | FileCheck %s --check-prefix=THUMB
5
6define i32 @t9(i32 %v) nounwind readnone {
7; ARM-LABEL: t9:
8; ARM:       @ %bb.0: @ %entry
9; ARM-NEXT:    add r0, r0, r0, lsl #3
10; ARM-NEXT:    mov pc, lr
11;
12; THUMB2-LABEL: t9:
13; THUMB2:       @ %bb.0: @ %entry
14; THUMB2-NEXT:    add.w r0, r0, r0, lsl #3
15; THUMB2-NEXT:    bx lr
16;
17; THUMB-LABEL: t9:
18; THUMB:       @ %bb.0: @ %entry
19; THUMB-NEXT:    movs r1, #9
20; THUMB-NEXT:    muls r0, r1, r0
21; THUMB-NEXT:    bx lr
22entry:
23	%0 = mul i32 %v, 9
24	ret i32 %0
25}
26
27define i32 @t7(i32 %v) nounwind readnone {
28; ARM-LABEL: t7:
29; ARM:       @ %bb.0: @ %entry
30; ARM-NEXT:    rsb r0, r0, r0, lsl #3
31; ARM-NEXT:    mov pc, lr
32;
33; THUMB2-LABEL: t7:
34; THUMB2:       @ %bb.0: @ %entry
35; THUMB2-NEXT:    rsb r0, r0, r0, lsl #3
36; THUMB2-NEXT:    bx lr
37;
38; THUMB-LABEL: t7:
39; THUMB:       @ %bb.0: @ %entry
40; THUMB-NEXT:    movs r1, #7
41; THUMB-NEXT:    muls r0, r1, r0
42; THUMB-NEXT:    bx lr
43entry:
44	%0 = mul i32 %v, 7
45	ret i32 %0
46}
47
48define i32 @t5(i32 %v) nounwind readnone {
49; ARM-LABEL: t5:
50; ARM:       @ %bb.0: @ %entry
51; ARM-NEXT:    add r0, r0, r0, lsl #2
52; ARM-NEXT:    mov pc, lr
53;
54; THUMB2-LABEL: t5:
55; THUMB2:       @ %bb.0: @ %entry
56; THUMB2-NEXT:    add.w r0, r0, r0, lsl #2
57; THUMB2-NEXT:    bx lr
58;
59; THUMB-LABEL: t5:
60; THUMB:       @ %bb.0: @ %entry
61; THUMB-NEXT:    movs r1, #5
62; THUMB-NEXT:    muls r0, r1, r0
63; THUMB-NEXT:    bx lr
64entry:
65        %0 = mul i32 %v, 5
66        ret i32 %0
67}
68
69define i32 @t3(i32 %v) nounwind readnone {
70; ARM-LABEL: t3:
71; ARM:       @ %bb.0: @ %entry
72; ARM-NEXT:    add r0, r0, r0, lsl #1
73; ARM-NEXT:    mov pc, lr
74;
75; THUMB2-LABEL: t3:
76; THUMB2:       @ %bb.0: @ %entry
77; THUMB2-NEXT:    add.w r0, r0, r0, lsl #1
78; THUMB2-NEXT:    bx lr
79;
80; THUMB-LABEL: t3:
81; THUMB:       @ %bb.0: @ %entry
82; THUMB-NEXT:    movs r1, #3
83; THUMB-NEXT:    muls r0, r1, r0
84; THUMB-NEXT:    bx lr
85entry:
86        %0 = mul i32 %v, 3
87        ret i32 %0
88}
89
90define i32 @t12288(i32 %v) nounwind readnone {
91; ARM-LABEL: t12288:
92; ARM:       @ %bb.0: @ %entry
93; ARM-NEXT:    add r0, r0, r0, lsl #1
94; ARM-NEXT:    lsl r0, r0, #12
95; ARM-NEXT:    mov pc, lr
96;
97; THUMB2-LABEL: t12288:
98; THUMB2:       @ %bb.0: @ %entry
99; THUMB2-NEXT:    add.w r0, r0, r0, lsl #1
100; THUMB2-NEXT:    lsls r0, r0, #12
101; THUMB2-NEXT:    bx lr
102;
103; THUMB-LABEL: t12288:
104; THUMB:       @ %bb.0: @ %entry
105; THUMB-NEXT:    movs r1, #3
106; THUMB-NEXT:    lsls r1, r1, #12
107; THUMB-NEXT:    muls r0, r1, r0
108; THUMB-NEXT:    bx lr
109entry:
110        %0 = mul i32 %v, 12288
111        ret i32 %0
112}
113
114define i32 @tn9(i32 %v) nounwind readnone {
115; ARM-LABEL: tn9:
116; ARM:       @ %bb.0: @ %entry
117; ARM-NEXT:    add r0, r0, r0, lsl #3
118; ARM-NEXT:    rsb r0, r0, #0
119; ARM-NEXT:    mov pc, lr
120;
121; THUMB2-LABEL: tn9:
122; THUMB2:       @ %bb.0: @ %entry
123; THUMB2-NEXT:    add.w r0, r0, r0, lsl #3
124; THUMB2-NEXT:    rsbs r0, r0, #0
125; THUMB2-NEXT:    bx lr
126;
127; THUMB-LABEL: tn9:
128; THUMB:       @ %bb.0: @ %entry
129; THUMB-NEXT:    movs r1, #8
130; THUMB-NEXT:    mvns r1, r1
131; THUMB-NEXT:    muls r0, r1, r0
132; THUMB-NEXT:    bx lr
133entry:
134        %0 = mul i32 %v, -9
135        ret i32 %0
136}
137
138define i32 @tn7(i32 %v) nounwind readnone {
139; ARM-LABEL: tn7:
140; ARM:       @ %bb.0: @ %entry
141; ARM-NEXT:    sub r0, r0, r0, lsl #3
142; ARM-NEXT:    mov pc, lr
143;
144; THUMB2-LABEL: tn7:
145; THUMB2:       @ %bb.0: @ %entry
146; THUMB2-NEXT:    sub.w r0, r0, r0, lsl #3
147; THUMB2-NEXT:    bx lr
148;
149; THUMB-LABEL: tn7:
150; THUMB:       @ %bb.0: @ %entry
151; THUMB-NEXT:    movs r1, #6
152; THUMB-NEXT:    mvns r1, r1
153; THUMB-NEXT:    muls r0, r1, r0
154; THUMB-NEXT:    bx lr
155entry:
156	%0 = mul i32 %v, -7
157	ret i32 %0
158}
159
160define i32 @tn5(i32 %v) nounwind readnone {
161; ARM-LABEL: tn5:
162; ARM:       @ %bb.0: @ %entry
163; ARM-NEXT:    add r0, r0, r0, lsl #2
164; ARM-NEXT:    rsb r0, r0, #0
165; ARM-NEXT:    mov pc, lr
166;
167; THUMB2-LABEL: tn5:
168; THUMB2:       @ %bb.0: @ %entry
169; THUMB2-NEXT:    add.w r0, r0, r0, lsl #2
170; THUMB2-NEXT:    rsbs r0, r0, #0
171; THUMB2-NEXT:    bx lr
172;
173; THUMB-LABEL: tn5:
174; THUMB:       @ %bb.0: @ %entry
175; THUMB-NEXT:    movs r1, #4
176; THUMB-NEXT:    mvns r1, r1
177; THUMB-NEXT:    muls r0, r1, r0
178; THUMB-NEXT:    bx lr
179entry:
180        %0 = mul i32 %v, -5
181        ret i32 %0
182}
183
184define i32 @tn3(i32 %v) nounwind readnone {
185; ARM-LABEL: tn3:
186; ARM:       @ %bb.0: @ %entry
187; ARM-NEXT:    sub r0, r0, r0, lsl #2
188; ARM-NEXT:    mov pc, lr
189;
190; THUMB2-LABEL: tn3:
191; THUMB2:       @ %bb.0: @ %entry
192; THUMB2-NEXT:    sub.w r0, r0, r0, lsl #2
193; THUMB2-NEXT:    bx lr
194;
195; THUMB-LABEL: tn3:
196; THUMB:       @ %bb.0: @ %entry
197; THUMB-NEXT:    movs r1, #2
198; THUMB-NEXT:    mvns r1, r1
199; THUMB-NEXT:    muls r0, r1, r0
200; THUMB-NEXT:    bx lr
201entry:
202; CHECK-LABEL: tn3:
203; CHECK: sub r0, r0, r0, lsl #2
204        %0 = mul i32 %v, -3
205        ret i32 %0
206}
207
208define i32 @tn12288(i32 %v) nounwind readnone {
209; ARM-LABEL: tn12288:
210; ARM:       @ %bb.0: @ %entry
211; ARM-NEXT:    sub r0, r0, r0, lsl #2
212; ARM-NEXT:    lsl r0, r0, #12
213; ARM-NEXT:    mov pc, lr
214;
215; THUMB2-LABEL: tn12288:
216; THUMB2:       @ %bb.0: @ %entry
217; THUMB2-NEXT:    sub.w r0, r0, r0, lsl #2
218; THUMB2-NEXT:    lsls r0, r0, #12
219; THUMB2-NEXT:    bx lr
220;
221; THUMB-LABEL: tn12288:
222; THUMB:       @ %bb.0: @ %entry
223; THUMB-NEXT:    ldr r1, .LCPI9_0
224; THUMB-NEXT:    muls r0, r1, r0
225; THUMB-NEXT:    bx lr
226; THUMB-NEXT:    .p2align 2
227; THUMB-NEXT:  @ %bb.1:
228; THUMB-NEXT:  .LCPI9_0:
229; THUMB-NEXT:    .long 4294955008 @ 0xffffd000
230entry:
231; CHECK-LABEL: tn12288:
232; CHECK: sub r0, r0, r0, lsl #2
233; CHECK: lsl{{.*}}#12
234        %0 = mul i32 %v, -12288
235        ret i32 %0
236}
237