1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=arm-eabi -mattr=+v6 %s -o - | FileCheck %s
3
4define i32 @test1(i32 %X) nounwind {
5; CHECK-LABEL: test1:
6; CHECK:       @ %bb.0:
7; CHECK-NEXT:    rev16 r0, r0
8; CHECK-NEXT:    bx lr
9        %tmp1 = lshr i32 %X, 8
10        %X15 = bitcast i32 %X to i32
11        %tmp4 = shl i32 %X15, 8
12        %tmp2 = and i32 %tmp1, 16711680
13        %tmp5 = and i32 %tmp4, -16777216
14        %tmp9 = and i32 %tmp1, 255
15        %tmp13 = and i32 %tmp4, 65280
16        %tmp6 = or i32 %tmp5, %tmp2
17        %tmp10 = or i32 %tmp6, %tmp13
18        %tmp14 = or i32 %tmp10, %tmp9
19        ret i32 %tmp14
20}
21
22define i32 @test2(i32 %X) nounwind {
23; CHECK-LABEL: test2:
24; CHECK:       @ %bb.0:
25; CHECK-NEXT:    revsh r0, r0
26; CHECK-NEXT:    bx lr
27        %tmp1 = lshr i32 %X, 8
28        %tmp1.upgrd.1 = trunc i32 %tmp1 to i16
29        %tmp3 = trunc i32 %X to i16
30        %tmp2 = and i16 %tmp1.upgrd.1, 255
31        %tmp4 = shl i16 %tmp3, 8
32        %tmp5 = or i16 %tmp2, %tmp4
33        %tmp5.upgrd.2 = sext i16 %tmp5 to i32
34        ret i32 %tmp5.upgrd.2
35}
36
37; rdar://9147637
38define i32 @test3(i16 zeroext %a) nounwind {
39; CHECK-LABEL: test3:
40; CHECK:       @ %bb.0: @ %entry
41; CHECK-NEXT:    revsh r0, r0
42; CHECK-NEXT:    bx lr
43entry:
44  %0 = tail call i16 @llvm.bswap.i16(i16 %a)
45  %1 = sext i16 %0 to i32
46  ret i32 %1
47}
48
49declare i16 @llvm.bswap.i16(i16) nounwind readnone
50
51define i32 @test4(i16 zeroext %a) nounwind {
52; CHECK-LABEL: test4:
53; CHECK:       @ %bb.0: @ %entry
54; CHECK-NEXT:    revsh r0, r0
55; CHECK-NEXT:    bx lr
56entry:
57  %conv = zext i16 %a to i32
58  %shr9 = lshr i16 %a, 8
59  %conv2 = zext i16 %shr9 to i32
60  %shl = shl nuw nsw i32 %conv, 8
61  %or = or i32 %conv2, %shl
62  %sext = shl i32 %or, 16
63  %conv8 = ashr exact i32 %sext, 16
64  ret i32 %conv8
65}
66
67; rdar://9609059
68define i32 @test5(i32 %i) nounwind readnone {
69; CHECK-LABEL: test5:
70; CHECK:       @ %bb.0: @ %entry
71; CHECK-NEXT:    revsh r0, r0
72; CHECK-NEXT:    bx lr
73entry:
74  %shl = shl i32 %i, 24
75  %shr = ashr exact i32 %shl, 16
76  %shr23 = lshr i32 %i, 8
77  %and = and i32 %shr23, 255
78  %or = or i32 %shr, %and
79  ret i32 %or
80}
81
82; rdar://9609108
83define i32 @test6(i32 %x) nounwind readnone {
84; CHECK-LABEL: test6:
85; CHECK:       @ %bb.0: @ %entry
86; CHECK-NEXT:    rev16 r0, r0
87; CHECK-NEXT:    bx lr
88entry:
89  %and = shl i32 %x, 8
90  %shl = and i32 %and, 65280
91  %and2 = lshr i32 %x, 8
92  %shr11 = and i32 %and2, 255
93  %shr5 = and i32 %and2, 16711680
94  %shl9 = and i32 %and, -16777216
95  %or = or i32 %shr5, %shl9
96  %or6 = or i32 %or, %shr11
97  %or10 = or i32 %or6, %shl
98  ret i32 %or10
99}
100
101; rdar://9164521
102define i32 @test7(i32 %a) nounwind readnone {
103; CHECK-LABEL: test7:
104; CHECK:       @ %bb.0: @ %entry
105; CHECK-NEXT:    rev r0, r0
106; CHECK-NEXT:    lsr r0, r0, #16
107; CHECK-NEXT:    bx lr
108entry:
109  %and = lshr i32 %a, 8
110  %shr3 = and i32 %and, 255
111  %and2 = shl i32 %a, 8
112  %shl = and i32 %and2, 65280
113  %or = or i32 %shr3, %shl
114  ret i32 %or
115}
116
117define i32 @test8(i32 %a) nounwind readnone {
118; CHECK-LABEL: test8:
119; CHECK:       @ %bb.0: @ %entry
120; CHECK-NEXT:    revsh r0, r0
121; CHECK-NEXT:    bx lr
122entry:
123  %and = lshr i32 %a, 8
124  %shr4 = and i32 %and, 255
125  %and2 = shl i32 %a, 8
126  %or = or i32 %shr4, %and2
127  %sext = shl i32 %or, 16
128  %conv3 = ashr exact i32 %sext, 16
129  ret i32 %conv3
130}
131
132; rdar://10750814
133define zeroext i16 @test9(i16 zeroext %v) nounwind readnone {
134; CHECK-LABEL: test9:
135; CHECK:       @ %bb.0: @ %entry
136; CHECK-NEXT:    rev16 r0, r0
137; CHECK-NEXT:    bx lr
138entry:
139  %conv = zext i16 %v to i32
140  %shr4 = lshr i32 %conv, 8
141  %shl = shl nuw nsw i32 %conv, 8
142  %or = or i32 %shr4, %shl
143  %conv3 = trunc i32 %or to i16
144  ret i16 %conv3
145}
146