1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=arm-eabi -mcpu=cortex-a8 | FileCheck %s
3
4define zeroext i1 @ne_neg1_and_ne_zero(i32 %x) nounwind {
5; CHECK-LABEL: ne_neg1_and_ne_zero:
6; CHECK:       @ %bb.0:
7; CHECK-NEXT:    add r1, r0, #1
8; CHECK-NEXT:    mov r0, #0
9; CHECK-NEXT:    cmp r1, #1
10; CHECK-NEXT:    movwhi r0, #1
11; CHECK-NEXT:    bx lr
12  %cmp1 = icmp ne i32 %x, -1
13  %cmp2 = icmp ne i32 %x, 0
14  %and = and i1 %cmp1, %cmp2
15  ret i1 %and
16}
17
18; PR32401 - https://bugs.llvm.org/show_bug.cgi?id=32401
19
20define zeroext i1 @and_eq(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
21; CHECK-LABEL: and_eq:
22; CHECK:       @ %bb.0:
23; CHECK: eor     r2, r2, r3
24; CHECK: eor     r0, r0, r1
25; CHECK: orr     r0, r0, r2
26; CHECK: clz     r0, r0
27; CHECK: lsr     r0, r0, #5
28; CHECK: bx      lr
29  %cmp1 = icmp eq i32 %a, %b
30  %cmp2 = icmp eq i32 %c, %d
31  %and = and i1 %cmp1, %cmp2
32  ret i1 %and
33}
34
35define zeroext i1 @or_ne(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
36; CHECK-LABEL: or_ne:
37; CHECK:       @ %bb.0:
38; CHECK-NEXT:    eor r2, r2, r3
39; CHECK-NEXT:    eor r0, r0, r1
40; CHECK-NEXT:    orrs r0, r0, r2
41; CHECK-NEXT:    movwne r0, #1
42; CHECK-NEXT:    bx lr
43  %cmp1 = icmp ne i32 %a, %b
44  %cmp2 = icmp ne i32 %c, %d
45  %or = or i1 %cmp1, %cmp2
46  ret i1 %or
47}
48
49define <4 x i1> @and_eq_vec(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d) nounwind {
50; CHECK-LABEL: and_eq_vec:
51; CHECK:       @ %bb.0:
52; CHECK-NEXT:    .save {r11, lr}
53; CHECK-NEXT:    push {r11, lr}
54; CHECK-NEXT:    vmov d19, r2, r3
55; CHECK-NEXT:    add r12, sp, #40
56; CHECK-NEXT:    add lr, sp, #8
57; CHECK-NEXT:    vmov d18, r0, r1
58; CHECK-NEXT:    vld1.64 {d16, d17}, [lr]
59; CHECK-NEXT:    add r0, sp, #24
60; CHECK-NEXT:    vld1.64 {d20, d21}, [r12]
61; CHECK-NEXT:    vceq.i32 q8, q9, q8
62; CHECK-NEXT:    vld1.64 {d22, d23}, [r0]
63; CHECK-NEXT:    vceq.i32 q9, q11, q10
64; CHECK-NEXT:    vand q8, q8, q9
65; CHECK-NEXT:    vmovn.i32 d16, q8
66; CHECK-NEXT:    vmov r0, r1, d16
67; CHECK-NEXT:    pop {r11, pc}
68  %cmp1 = icmp eq <4 x i32> %a, %b
69  %cmp2 = icmp eq <4 x i32> %c, %d
70  %and = and <4 x i1> %cmp1, %cmp2
71  ret <4 x i1> %and
72}
73
74