1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=armv8 | FileCheck %s
3define <4 x i32> @test(<4 x i32> %m) {
4; CHECK-LABEL: test:
5; CHECK:       @ %bb.0: @ %entry
6; CHECK-NEXT:    vmov d17, r2, r3
7; CHECK-NEXT:    vmov d16, r0, r1
8; CHECK-NEXT:    vshl.i32 q8, q8, #24
9; CHECK-NEXT:    vshr.s32 q8, q8, #24
10; CHECK-NEXT:    vmov r0, r1, d16
11; CHECK-NEXT:    vmov r2, r3, d17
12; CHECK-NEXT:    bx lr
13entry:
14  %shl = shl <4 x i32> %m, <i32 24, i32 24, i32 24, i32 24>
15  %shr = ashr exact <4 x i32> %shl, <i32 24, i32 24, i32 24, i32 24>
16  ret <4 x i32> %shr
17}
18