1; RUN: llc -mtriple armv6t2 %s -o - | FileCheck %s
2; RUN: llc -mtriple thumbv6t2 %s -o - | FileCheck %s --check-prefix=CHECK-T2
3; RUN: llc -mtriple armv7 %s -o - | FileCheck %s
4; RUN: llc -mtriple thumbv7 %s -o - | FileCheck %s --check-prefix=CHECK-T2
5; RUN: llc -mtriple thumbv7m %s -o - | FileCheck %s --check-prefix=CHECK-T2
6; RUN: llc -mtriple thumbv8m.main %s -o - | FileCheck %s --check-prefix=CHECK-T2
7
8; CHECK-LABEL: unfold1
9; CHECK-NOT: mov
10; CHECK: orr r0, r0, #255
11; CHECK: add r0, r1, r0, lsl #1
12; CHECK-T2-NOT: mov
13; CHECK-T2: orr r0, r0, #255
14; CHECK-T2: add.w r0, r1, r0, lsl #1
15define arm_aapcscc i32 @unfold1(i32 %a, i32 %b) {
16entry:
17  %or = shl i32 %a, 1
18  %shl = or i32 %or, 510
19  %add = add nsw i32 %shl, %b
20  ret i32 %add
21}
22
23; CHECK-LABEL: unfold2
24; CHECK-NOT: mov
25; CHECK: orr r0, r0, #4080
26; CHECK: sub r0, r1, r0, lsl #2
27; CHECK-T2-NOT: mov
28; CHECK-T2: orr r0, r0, #4080
29; CHECK-T2: sub.w r0, r1, r0, lsl #2
30define arm_aapcscc i32 @unfold2(i32 %a, i32 %b) {
31entry:
32  %or = shl i32 %a, 2
33  %shl = or i32 %or, 16320
34  %sub = sub nsw i32 %b, %shl
35  ret i32 %sub
36}
37
38; CHECK-LABEL: unfold3
39; CHECK-NOT: mov
40; CHECK: orr r0, r0, #65280
41; CHECK: and r0, r1, r0, lsl #4
42; CHECK-T2-NOT: mov
43; CHECK-T2: orr r0, r0, #65280
44; CHECK-T2: and.w r0, r1, r0, lsl #4
45define arm_aapcscc i32 @unfold3(i32 %a, i32 %b) {
46entry:
47  %or = shl i32 %a, 4
48  %shl = or i32 %or, 1044480
49  %and = and i32 %shl, %b
50  ret i32 %and
51}
52
53; CHECK-LABEL: unfold4
54; CHECK-NOT: mov
55; CHECK: orr r0, r0, #1044480
56; CHECK: eor r0, r1, r0, lsl #5
57; CHECK-T2-NOT: mov
58; CHECK-T2: orr r0, r0, #1044480
59; CHECK-T2: eor.w r0, r1, r0, lsl #5
60define arm_aapcscc i32 @unfold4(i32 %a, i32 %b) {
61entry:
62  %or = shl i32 %a, 5
63  %shl = or i32 %or, 33423360
64  %xor = xor i32 %shl, %b
65  ret i32 %xor
66}
67
68; CHECK-LABEL: unfold5
69; CHECK-NOT: mov
70; CHECK: add r0, r0, #496
71; CHECK: orr r0, r1, r0, lsl #6
72; CHECK-T2: add.w r0, r0, #496
73; CHECK-T2: orr.w r0, r1, r0, lsl #6
74define arm_aapcscc i32 @unfold5(i32 %a, i32 %b) {
75entry:
76  %add = shl i32 %a, 6
77  %shl = add i32 %add, 31744
78  %or = or i32 %shl, %b
79  ret i32 %or
80}
81
82; CHECK-LABEL: unfold6
83; CHECK-NOT: mov
84; CHECK: add r0, r0, #7936
85; CHECK: and r0, r1, r0, lsl #8
86; CHECK-T2-NOT: mov
87; CHECK-T2: add.w r0, r0, #7936
88; CHECK-T2: and.w r0, r1, r0, lsl #8
89define arm_aapcscc i32 @unfold6(i32 %a, i32 %b) {
90entry:
91  %add = shl i32 %a, 8
92  %shl = add i32 %add, 2031616
93  %and = and i32 %shl, %b
94  ret i32 %and
95}
96
97; CHECK-LABEL: unfold7
98; CHECK-NOT: mov
99; CHECK: and r0, r0, #256
100; CHECK: add r0, r1, r0, lsl #1
101; CHECK-T2-NOT: mov
102; CHECK-T2: and r0, r0, #256
103; CHECK-T2: add.w r0, r1, r0, lsl #1
104define arm_aapcscc i32 @unfold7(i32 %a, i32 %b) {
105entry:
106  %shl = shl i32 %a, 1
107  %and = and i32 %shl, 512
108  %add = add nsw i32 %and, %b
109  ret i32 %add
110}
111
112; CHECK-LABEL: unfold8
113; CHECK-NOT: mov
114; CHECK: add r0, r0, #126976
115; CHECK: eor r0, r1, r0, lsl #9
116; CHECK-T2-NOT: mov
117; CHECK-T2: add.w r0, r0, #126976
118; CHECK-T2: eor.w r0, r1, r0, lsl #9
119define arm_aapcscc i32 @unfold8(i32 %a, i32 %b) {
120entry:
121  %add = shl i32 %a, 9
122  %shl = add i32 %add, 65011712
123  %xor = xor i32 %shl, %b
124  ret i32 %xor
125}
126
127; CHECK-LABEL: unfold9
128; CHECK-NOT: mov
129; CHECK: eor r0, r0, #255
130; CHECK: add r0, r1, r0, lsl #1
131; CHECK-T2-NOT: mov
132; CHECK-T2: eor r0, r0, #255
133; CHECK-T2: add.w r0, r1, r0, lsl #1
134define arm_aapcscc i32 @unfold9(i32 %a, i32 %b) {
135entry:
136  %shl = shl i32 %a, 1
137  %xor = xor i32 %shl, 510
138  %add = add nsw i32 %xor, %b
139  ret i32 %add
140}
141
142; CHECK-LABEL: unfold10
143; CHECK-NOT: mov r2
144; CHECK: orr r2, r0, #4080
145; CHECK: cmp r1, r2, lsl #10
146; CHECK-T2-NOT: mov.w r2
147; CHECK-T2: orr r2, r0, #4080
148; CHECK-T2: cmp.w r1, r2, lsl #10
149define arm_aapcscc i32 @unfold10(i32 %a, i32 %b) {
150entry:
151  %or = shl i32 %a, 10
152  %shl = or i32 %or, 4177920
153  %cmp = icmp sgt i32 %shl, %b
154  %conv = zext i1 %cmp to i32
155  ret i32 %conv
156}
157
158; CHECK-LABEL: unfold11
159; CHECK-NOT: mov r2
160; CHECK: add r2, r0, #7936
161; CHECK: cmp r1, r2, lsl #11
162; CHECK-T2-NOT: mov.w r2
163; CHECK-T2: add.w r2, r0, #7936
164; CHECK-T2: cmp.w r1, r2, lsl #11
165define arm_aapcscc i32 @unfold11(i32 %a, i32 %b) {
166entry:
167  %add = shl i32 %a, 11
168  %shl = add i32 %add, 16252928
169  %cmp = icmp sgt i32 %shl, %b
170  %conv = zext i1 %cmp to i32
171  ret i32 %conv
172}
173
174