1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=armv6-eabi %s -o - | FileCheck %s
3; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+dsp %s -o - | FileCheck %s
4
5define arm_aapcs_vfpcc i32 @usat_lsl(i32 %num){
6; CHECK-LABEL:  usat_lsl
7; CHECK:        @ %bb.0: @ %entry
8; CHECK-NEXT: 	usat	r0, #7, r0, lsl #2
9; CHECK-NEXT:   bx	lr
10entry:
11  %shl = shl i32 %num, 2
12  %0 = tail call i32 @llvm.arm.usat(i32 %shl, i32 7)
13  ret i32 %0
14}
15
16define arm_aapcs_vfpcc i32 @usat_asr(i32 %num){
17; CHECK-LABEL:  usat_asr
18; CHECK:        @ %bb.0: @ %entry
19; CHECK-NEXT:   usat	r0, #7, r0, asr #2
20; CHECK-NEXT:   bx	lr
21entry:
22  %shr = ashr i32 %num, 2
23  %0 = tail call i32 @llvm.arm.usat(i32 %shr, i32 7)
24  ret i32 %0
25}
26
27define arm_aapcs_vfpcc i32 @usat_lsl2(i32 %num){
28; CHECK-LABEL: usat_lsl2:
29; CHECK:       @ %bb.0: @ %entry
30; CHECK-NEXT:    usat r0, #15, r0, lsl #15
31; CHECK-NEXT:    bx lr
32entry:
33  %shl = shl nsw i32 %num, 15
34  %0 = icmp sgt i32 %shl, 0
35  %1 = select i1 %0, i32 %shl, i32 0
36  %2 = icmp slt i32 %1, 32767
37  %3 = select i1 %2, i32 %1, i32 32767
38  ret i32 %3
39}
40
41define arm_aapcs_vfpcc i32 @usat_asr2(i32 %num){
42; CHECK-LABEL: usat_asr2:
43; CHECK:       @ %bb.0: @ %entry
44; CHECK-NEXT:    usat r0, #15, r0, asr #15
45; CHECK-NEXT:    bx lr
46entry:
47  %shr = ashr i32 %num, 15
48  %0 = icmp sgt i32 %shr, 0
49  %1 = select i1 %0, i32 %shr, i32 0
50  %2 = icmp slt i32 %1, 32767
51  %3 = select i1 %2, i32 %1, i32 32767
52  ret i32 %3
53}
54
55declare i32 @llvm.arm.usat(i32, i32)
56