1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=arm-eabi -mattr=+v6 | FileCheck %s --check-prefixes=CHECK,CHECK-V6
3; RUN: llc < %s -mtriple=arm-eabi -mattr=+v7 | FileCheck %s --check-prefixes=CHECK,CHECK-V7
4
5define zeroext i8 @test1(i32 %A.u) {
6; CHECK-LABEL: test1:
7; CHECK:       @ %bb.0:
8; CHECK-NEXT:    uxtb r0, r0
9; CHECK-NEXT:    bx lr
10    %B.u = trunc i32 %A.u to i8
11    ret i8 %B.u
12}
13
14define zeroext i32 @test2(i32 %A.u, i32 %B.u) {
15; CHECK-LABEL: test2:
16; CHECK:       @ %bb.0:
17; CHECK-NEXT:    uxtab r0, r0, r1
18; CHECK-NEXT:    bx lr
19    %C.u = trunc i32 %B.u to i8
20    %D.u = zext i8 %C.u to i32
21    %E.u = add i32 %A.u, %D.u
22    ret i32 %E.u
23}
24
25define zeroext i32 @test3(i32 %A.u) {
26; CHECK-V6-LABEL: test3:
27; CHECK-V6:       @ %bb.0:
28; CHECK-V6-NEXT:    lsr r0, r0, #8
29; CHECK-V6-NEXT:    uxth r0, r0
30; CHECK-V6-NEXT:    bx lr
31;
32; CHECK-V7-LABEL: test3:
33; CHECK-V7:       @ %bb.0:
34; CHECK-V7-NEXT:    ubfx r0, r0, #8, #16
35; CHECK-V7-NEXT:    bx lr
36    %B.u = lshr i32 %A.u, 8
37    %C.u = shl i32 %A.u, 24
38    %D.u = or i32 %B.u, %C.u
39    %E.u = trunc i32 %D.u to i16
40    %F.u = zext i16 %E.u to i32
41    ret i32 %F.u
42}
43
44define zeroext i32 @test4(i32 %A.u) {
45; CHECK-V6-LABEL: test4:
46; CHECK-V6:       @ %bb.0:
47; CHECK-V6-NEXT:    lsr r0, r0, #8
48; CHECK-V6-NEXT:    uxtb r0, r0
49; CHECK-V6-NEXT:    bx lr
50;
51; CHECK-V7-LABEL: test4:
52; CHECK-V7:       @ %bb.0:
53; CHECK-V7-NEXT:    ubfx r0, r0, #8, #8
54; CHECK-V7-NEXT:    bx lr
55    %B.u = lshr i32 %A.u, 8
56    %C.u = shl i32 %A.u, 24
57    %D.u = or i32 %B.u, %C.u
58    %E.u = trunc i32 %D.u to i8
59    %F.u = zext i8 %E.u to i32
60    ret i32 %F.u
61}
62
63define zeroext i16 @test5(i32 %A.u) {
64; CHECK-LABEL: test5:
65; CHECK:       @ %bb.0:
66; CHECK-NEXT:    uxth r0, r0
67; CHECK-NEXT:    bx lr
68    %B.u = trunc i32 %A.u to i16
69    ret i16 %B.u
70}
71
72define zeroext i32 @test6(i32 %A.u, i32 %B.u) {
73; CHECK-LABEL: test6:
74; CHECK:       @ %bb.0:
75; CHECK-NEXT:    uxtah r0, r0, r1
76; CHECK-NEXT:    bx lr
77    %C.u = trunc i32 %B.u to i16
78    %D.u = zext i16 %C.u to i32
79    %E.u = add i32 %A.u, %D.u
80    ret i32 %E.u
81}
82
83define zeroext i32 @test7(i32 %A, i32 %X) {
84; CHECK-LABEL: test7:
85; CHECK:       @ %bb.0:
86; CHECK-NEXT:    uxtab r0, r1, r0, ror #8
87; CHECK-NEXT:    bx lr
88  %B = lshr i32 %A, 8
89  %C = shl i32 %A, 24
90  %D = or i32 %B, %C
91  %E = trunc i32 %D to i8
92  %F = zext i8 %E to i32
93  %G = add i32 %F, %X
94  ret i32 %G
95}
96
97define zeroext i32 @test8(i32 %A, i32 %X) {
98; CHECK-LABEL: test8:
99; CHECK:       @ %bb.0:
100; CHECK-NEXT:    uxtab r0, r1, r0, ror #16
101; CHECK-NEXT:    bx lr
102  %B = lshr i32 %A, 16
103  %C = shl i32 %A, 16
104  %D = or i32 %B, %C
105  %E = trunc i32 %D to i8
106  %F = zext i8 %E to i32
107  %G = add i32 %F, %X
108  ret i32 %G
109}
110
111define zeroext i32 @test9(i32 %A, i32 %X) {
112; CHECK-LABEL: test9:
113; CHECK:       @ %bb.0:
114; CHECK-NEXT:    uxtah r0, r1, r0, ror #8
115; CHECK-NEXT:    bx lr
116  %B = lshr i32 %A, 8
117  %C = shl i32 %A, 24
118  %D = or i32 %B, %C
119  %E = trunc i32 %D to i16
120  %F = zext i16 %E to i32
121  %G = add i32 %F, %X
122  ret i32 %G
123}
124
125define zeroext i32 @test10(i32 %A, i32 %X) {
126; CHECK-LABEL: test10:
127; CHECK:       @ %bb.0:
128; CHECK-NEXT:    uxtah r0, r1, r0, ror #24
129; CHECK-NEXT:    bx lr
130  %B = lshr i32 %A, 24
131  %C = shl i32 %A, 8
132  %D = or i32 %B, %C
133  %E = trunc i32 %D to i16
134  %F = zext i16 %E to i32
135  %G = add i32 %F, %X
136  ret i32 %G
137}
138
139define zeroext i32 @test11(i32 %A, i32 %X) {
140; CHECK-LABEL: test11:
141; CHECK:       @ %bb.0:
142; CHECK-NEXT:    uxtab r0, r1, r0
143; CHECK-NEXT:    bx lr
144  %B = and i32 %A, 255
145  %add = add i32 %X, %B
146  ret i32 %add
147}
148
149define zeroext i32 @test12(i32 %A, i32 %X) {
150; CHECK-LABEL: test12:
151; CHECK:       @ %bb.0:
152; CHECK-NEXT:    uxtab r0, r1, r0, ror #8
153; CHECK-NEXT:    bx lr
154  %B = lshr i32 %A, 8
155  %and = and i32 %B, 255
156  %add = add i32 %and, %X
157  ret i32 %add
158}
159
160define zeroext i32 @test13(i32 %A, i32 %X) {
161; CHECK-LABEL: test13:
162; CHECK:       @ %bb.0:
163; CHECK-NEXT:    uxtab r0, r1, r0, ror #16
164; CHECK-NEXT:    bx lr
165  %B = lshr i32 %A, 16
166  %and = and i32 %B, 255
167  %add = add i32 %and, %X
168  ret i32 %add
169}
170
171define zeroext i32 @test14(i32 %A, i32 %X) {
172; CHECK-LABEL: test14:
173; CHECK:       @ %bb.0:
174; CHECK-NEXT:    uxtah r0, r1, r0
175; CHECK-NEXT:    bx lr
176  %B = and i32 %A, 65535
177  %add = add i32 %X, %B
178  ret i32 %add
179}
180
181define zeroext i32 @test15(i32 %A, i32 %X) {
182; CHECK-LABEL: test15:
183; CHECK:       @ %bb.0:
184; CHECK-NEXT:    uxtah r0, r1, r0, ror #8
185; CHECK-NEXT:    bx lr
186  %B = lshr i32 %A, 8
187  %and = and i32 %B, 65535
188  %add = add i32 %and, %X
189  ret i32 %add
190}
191
192define zeroext i32 @test16(i32 %A, i32 %X) {
193; CHECK-LABEL: test16:
194; CHECK:       @ %bb.0:
195; CHECK-NEXT:    uxtah r0, r1, r0, ror #24
196; CHECK-NEXT:    bx lr
197  %B = lshr i32 %A, 24
198  %C = shl i32 %A, 8
199  %D = or i32 %B, %C
200  %E = and i32 %D, 65535
201  %F = add i32 %E, %X
202  ret i32 %F
203}
204