1; RUN: llc < %s -march=avr | FileCheck %s
2
3; At one point, the 16-vit atomic load/store operations we defined in TableGen
4; to use 'PTRREGS', but the pseudo expander would generate LDDW/STDW instructions.
5;
6; This would sometimes cause codegen to fail because LDDW requires 'PTRDISPREGS', and
7; so if we attempted to generate an atomic operation on the X register, it would hit
8; an assertion;
9
10%AtomicI16 = type { %UnsafeCell, [0 x i8] }
11%UnsafeCell = type { i16, [0 x i8] }
12
13; CHECK-LABEL: foo
14define i8 @foo(%AtomicI16*) {
15start:
16
17; We should not be generating atomics that use the X register, they will fail when emitting MC.
18; CHECK-NOT: X
19  %1 = getelementptr inbounds %AtomicI16, %AtomicI16* %0, i16 0, i32 0, i32 0
20  %2 = load atomic i16, i16* %1 seq_cst, align 2
21  ret i8 0
22}
23
24