1; RUN: llc -march=hexagon < %s | FileCheck %s
2
3; CHECK-LABEL: test_00
4; CHECK: [[R00:r[0-9]+]] = ##16843009
5; CHECK: [[V00:v[0-9]+]] = vsplat([[R00]])
6; CHECK: v0 = vdelta(v0,[[V00]])
7define <32 x i16> @test_00(<32 x i16> %a0) #0 {
8  %v0 = call <32 x i16> @llvm.bswap.v32i16(<32 x i16> %a0)
9  ret <32 x i16> %v0
10}
11
12; CHECK-LABEL: test_01
13; CHECK: [[R01:r[0-9]+]] = ##50529027
14; CHECK: [[V01:v[0-9]+]] = vsplat([[R01]])
15; CHECK: v0 = vdelta(v0,[[V01]])
16define <16 x i32> @test_01(<16 x i32> %a0) #0 {
17  %v0 = call <16 x i32> @llvm.bswap.v16i32(<16 x i32> %a0)
18  ret <16 x i32> %v0
19}
20
21; CHECK-LABEL: test_10
22; CHECK: [[R10:r[0-9]+]] = ##16843009
23; CHECK: [[V10:v[0-9]+]] = vsplat([[R10]])
24; CHECK: v0 = vdelta(v0,[[V10]])
25define <64 x i16> @test_10(<64 x i16> %a0) #1 {
26  %v0 = call <64 x i16> @llvm.bswap.v64i16(<64 x i16> %a0)
27  ret <64 x i16> %v0
28}
29
30; CHECK-LABEL: test_11
31; CHECK: [[R11:r[0-9]+]] = ##50529027
32; CHECK: [[V11:v[0-9]+]] = vsplat([[R11]])
33; CHECK: v0 = vdelta(v0,[[V11]])
34define <32 x i32> @test_11(<32 x i32> %a0) #1 {
35  %v0 = call <32 x i32> @llvm.bswap.v32i32(<32 x i32> %a0)
36  ret <32 x i32> %v0
37}
38
39declare <32 x i16> @llvm.bswap.v32i16(<32 x i16>) #0
40declare <16 x i32> @llvm.bswap.v16i32(<16 x i32>) #0
41declare <64 x i16> @llvm.bswap.v64i16(<64 x i16>) #1
42declare <32 x i32> @llvm.bswap.v32i32(<32 x i32>) #1
43
44attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
45attributes #1 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" }
46