1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -march=hexagon < %s | FileCheck %s
3
4; Check that selection (based on i1) between vector predicates works.
5define <128 x i8> @f0(<128 x i8> %a0, <128 x i8> %a1, <128 x i8> %a2, <128 x i8> %a3, i32 %a4) #0 {
6; CHECK-LABEL: f0:
7; CHECK:       // %bb.0:
8; CHECK-NEXT:    {
9; CHECK-NEXT:     q0 = vcmp.gt(v0.b,v1.b)
10; CHECK-NEXT:    }
11; CHECK-NEXT:    {
12; CHECK-NEXT:     q1 = vcmp.gt(v1.b,v2.b)
13; CHECK-NEXT:    }
14; CHECK-NEXT:    {
15; CHECK-NEXT:     r2 = #-1
16; CHECK-NEXT:    }
17; CHECK-NEXT:    {
18; CHECK-NEXT:     p0 = cmp.gt(r0,#0)
19; CHECK-NEXT:    }
20; CHECK-NEXT:    {
21; CHECK-NEXT:     v0 = vand(q1,r2)
22; CHECK-NEXT:    }
23; CHECK-NEXT:    {
24; CHECK-NEXT:     v2 = vand(q0,r2)
25; CHECK-NEXT:    }
26; CHECK-NEXT:    {
27; CHECK-NEXT:     if (p0) v0 = v2
28; CHECK-NEXT:    }
29; CHECK-NEXT:    {
30; CHECK-NEXT:     q3 = vand(v0,r2)
31; CHECK-NEXT:    }
32; CHECK-NEXT:    {
33; CHECK-NEXT:     v0 = vmux(q3,v1,v3)
34; CHECK-NEXT:    }
35; CHECK-NEXT:    {
36; CHECK-NEXT:     jumpr r31
37; CHECK-NEXT:    }
38  %v0 = icmp sgt <128 x i8> %a0, %a1
39  %v1 = icmp sgt <128 x i8> %a1, %a2
40  %v2 = icmp sgt i32 %a4, 0
41  %v3 = select i1 %v2, <128 x i1> %v0, <128 x i1> %v1
42  %v4 = select <128 x i1> %v3, <128 x i8> %a1, <128 x i8> %a3
43  ret <128 x i8> %v4
44}
45
46define <64 x i16> @f1(<64 x i16> %a0, <64 x i16> %a1, <64 x i16> %a2, <64 x i16> %a3, i32 %a4) #0 {
47; CHECK-LABEL: f1:
48; CHECK:       // %bb.0:
49; CHECK-NEXT:    {
50; CHECK-NEXT:     q0 = vcmp.gt(v0.h,v1.h)
51; CHECK-NEXT:    }
52; CHECK-NEXT:    {
53; CHECK-NEXT:     q1 = vcmp.gt(v1.h,v2.h)
54; CHECK-NEXT:    }
55; CHECK-NEXT:    {
56; CHECK-NEXT:     r2 = #-1
57; CHECK-NEXT:    }
58; CHECK-NEXT:    {
59; CHECK-NEXT:     p0 = cmp.gt(r0,#0)
60; CHECK-NEXT:    }
61; CHECK-NEXT:    {
62; CHECK-NEXT:     v0 = vand(q1,r2)
63; CHECK-NEXT:    }
64; CHECK-NEXT:    {
65; CHECK-NEXT:     v2 = vand(q0,r2)
66; CHECK-NEXT:    }
67; CHECK-NEXT:    {
68; CHECK-NEXT:     if (p0) v0 = v2
69; CHECK-NEXT:    }
70; CHECK-NEXT:    {
71; CHECK-NEXT:     q3 = vand(v0,r2)
72; CHECK-NEXT:    }
73; CHECK-NEXT:    {
74; CHECK-NEXT:     v0 = vmux(q3,v1,v3)
75; CHECK-NEXT:    }
76; CHECK-NEXT:    {
77; CHECK-NEXT:     jumpr r31
78; CHECK-NEXT:    }
79  %v0 = icmp sgt <64 x i16> %a0, %a1
80  %v1 = icmp sgt <64 x i16> %a1, %a2
81  %v2 = icmp sgt i32 %a4, 0
82  %v3 = select i1 %v2, <64 x i1> %v0, <64 x i1> %v1
83  %v4 = select <64 x i1> %v3, <64 x i16> %a1, <64 x i16> %a3
84  ret <64 x i16> %v4
85}
86
87define <32 x i32> @f2(<32 x i32> %a0, <32 x i32> %a1, <32 x i32> %a2, <32 x i32> %a3, i32 %a4) #0 {
88; CHECK-LABEL: f2:
89; CHECK:       // %bb.0:
90; CHECK-NEXT:    {
91; CHECK-NEXT:     q0 = vcmp.gt(v0.w,v1.w)
92; CHECK-NEXT:    }
93; CHECK-NEXT:    {
94; CHECK-NEXT:     q1 = vcmp.gt(v1.w,v2.w)
95; CHECK-NEXT:    }
96; CHECK-NEXT:    {
97; CHECK-NEXT:     r2 = #-1
98; CHECK-NEXT:    }
99; CHECK-NEXT:    {
100; CHECK-NEXT:     p0 = cmp.gt(r0,#0)
101; CHECK-NEXT:    }
102; CHECK-NEXT:    {
103; CHECK-NEXT:     v0 = vand(q1,r2)
104; CHECK-NEXT:    }
105; CHECK-NEXT:    {
106; CHECK-NEXT:     v2 = vand(q0,r2)
107; CHECK-NEXT:    }
108; CHECK-NEXT:    {
109; CHECK-NEXT:     if (p0) v0 = v2
110; CHECK-NEXT:    }
111; CHECK-NEXT:    {
112; CHECK-NEXT:     q3 = vand(v0,r2)
113; CHECK-NEXT:    }
114; CHECK-NEXT:    {
115; CHECK-NEXT:     v0 = vmux(q3,v1,v3)
116; CHECK-NEXT:    }
117; CHECK-NEXT:    {
118; CHECK-NEXT:     jumpr r31
119; CHECK-NEXT:    }
120  %v0 = icmp sgt <32 x i32> %a0, %a1
121  %v1 = icmp sgt <32 x i32> %a1, %a2
122  %v2 = icmp sgt i32 %a4, 0
123  %v3 = select i1 %v2, <32 x i1> %v0, <32 x i1> %v1
124  %v4 = select <32 x i1> %v3, <32 x i32> %a1, <32 x i32> %a3
125  ret <32 x i32> %v4
126}
127
128; Selection of vector predicates first converts them into regular vectors.
129; Check that all-true and all-false bool vectors are optimized into splat(-1)
130; and vxor(v,v).
131define <128 x i8> @f3(<128 x i8> %a0, <128 x i8> %a1, i32 %a2) #0 {
132; CHECK-LABEL: f3:
133; CHECK:       // %bb.0:
134; CHECK-NEXT:    {
135; CHECK-NEXT:     r2 = #-1
136; CHECK-NEXT:    }
137; CHECK-NEXT:    {
138; CHECK-NEXT:     p0 = cmp.gt(r0,#0)
139; CHECK-NEXT:    }
140; CHECK-NEXT:    {
141; CHECK-NEXT:     v2 = vxor(v2,v2)
142; CHECK-NEXT:    }
143; CHECK-NEXT:    {
144; CHECK-NEXT:     v3 = vsplat(r2)
145; CHECK-NEXT:    }
146; CHECK-NEXT:    {
147; CHECK-NEXT:     if (p0) v2 = v3
148; CHECK-NEXT:    }
149; CHECK-NEXT:    {
150; CHECK-NEXT:     q0 = vand(v2,r2)
151; CHECK-NEXT:    }
152; CHECK-NEXT:    {
153; CHECK-NEXT:     v0 = vmux(q0,v0,v1)
154; CHECK-NEXT:    }
155; CHECK-NEXT:    {
156; CHECK-NEXT:     jumpr r31
157; CHECK-NEXT:    }
158  %v0 = insertelement <128 x i1> undef, i1 true, i32 0
159  %v1 = shufflevector <128 x i1> %v0, <128 x i1> undef, <128 x i32> zeroinitializer
160  %v2 = icmp sgt i32 %a2, 0
161  %v3 = select i1 %v2, <128 x i1> %v1, <128 x i1> zeroinitializer
162  %v4 = select <128 x i1> %v3, <128 x i8> %a0, <128 x i8> %a1
163  ret <128 x i8> %v4
164}
165
166define <64 x i16> @f4(<64 x i16> %a0, <64 x i16> %a1, i32 %a2) #0 {
167; CHECK-LABEL: f4:
168; CHECK:       // %bb.0:
169; CHECK-NEXT:    {
170; CHECK-NEXT:     r2 = #-1
171; CHECK-NEXT:    }
172; CHECK-NEXT:    {
173; CHECK-NEXT:     p0 = cmp.gt(r0,#0)
174; CHECK-NEXT:    }
175; CHECK-NEXT:    {
176; CHECK-NEXT:     v2 = vxor(v2,v2)
177; CHECK-NEXT:    }
178; CHECK-NEXT:    {
179; CHECK-NEXT:     v3 = vsplat(r2)
180; CHECK-NEXT:    }
181; CHECK-NEXT:    {
182; CHECK-NEXT:     if (p0) v2 = v3
183; CHECK-NEXT:    }
184; CHECK-NEXT:    {
185; CHECK-NEXT:     q0 = vand(v2,r2)
186; CHECK-NEXT:    }
187; CHECK-NEXT:    {
188; CHECK-NEXT:     v0 = vmux(q0,v0,v1)
189; CHECK-NEXT:    }
190; CHECK-NEXT:    {
191; CHECK-NEXT:     jumpr r31
192; CHECK-NEXT:    }
193  %v0 = insertelement <64 x i1> undef, i1 true, i32 0
194  %v1 = shufflevector <64 x i1> %v0, <64 x i1> undef, <64 x i32> zeroinitializer
195  %v2 = icmp sgt i32 %a2, 0
196  %v3 = select i1 %v2, <64 x i1> %v1, <64 x i1> zeroinitializer
197  %v4 = select <64 x i1> %v3, <64 x i16> %a0, <64 x i16> %a1
198  ret <64 x i16> %v4
199}
200
201define <32 x i32> @f5(<32 x i32> %a0, <32 x i32> %a1, i32 %a2) #0 {
202; CHECK-LABEL: f5:
203; CHECK:       // %bb.0:
204; CHECK-NEXT:    {
205; CHECK-NEXT:     r2 = #-1
206; CHECK-NEXT:    }
207; CHECK-NEXT:    {
208; CHECK-NEXT:     p0 = cmp.gt(r0,#0)
209; CHECK-NEXT:    }
210; CHECK-NEXT:    {
211; CHECK-NEXT:     v2 = vxor(v2,v2)
212; CHECK-NEXT:    }
213; CHECK-NEXT:    {
214; CHECK-NEXT:     v3 = vsplat(r2)
215; CHECK-NEXT:    }
216; CHECK-NEXT:    {
217; CHECK-NEXT:     if (p0) v2 = v3
218; CHECK-NEXT:    }
219; CHECK-NEXT:    {
220; CHECK-NEXT:     q0 = vand(v2,r2)
221; CHECK-NEXT:    }
222; CHECK-NEXT:    {
223; CHECK-NEXT:     v0 = vmux(q0,v0,v1)
224; CHECK-NEXT:    }
225; CHECK-NEXT:    {
226; CHECK-NEXT:     jumpr r31
227; CHECK-NEXT:    }
228  %v0 = insertelement <32 x i1> undef, i1 true, i32 0
229  %v1 = shufflevector <32 x i1> %v0, <32 x i1> undef, <32 x i32> zeroinitializer
230  %v2 = icmp sgt i32 %a2, 0
231  %v3 = select i1 %v2, <32 x i1> %v1, <32 x i1> zeroinitializer
232  %v4 = select <32 x i1> %v3, <32 x i32> %a0, <32 x i32> %a1
233  ret <32 x i32> %v4
234}
235
236attributes #0 = { nounwind "target-cpu"="hexagonv66" "target-features"="+hvx,+hvx-length128b,-packets" }
237
238