1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -march=hexagon < %s | FileCheck %s
3
4; Splat immediate, 8-bit, v60
5define <128 x i8> @f0() #0 {
6; CHECK-LABEL: f0:
7; CHECK:       // %bb.0:
8; CHECK-NEXT:    {
9; CHECK-NEXT:     r0 = ##2139062143
10; CHECK-NEXT:    }
11; CHECK-NEXT:    {
12; CHECK-NEXT:     v0 = vsplat(r0)
13; CHECK-NEXT:     jumpr r31
14; CHECK-NEXT:    }
15  %v0 = insertelement <128 x i8> undef, i8 127, i32 0
16  %v1 = shufflevector <128 x i8> %v0, <128 x i8> undef, <128 x i32> zeroinitializer
17  ret <128 x i8> %v1
18}
19
20; Splat immediate, 16 bit, v60
21define <64 x i16> @f1() #0 {
22; CHECK-LABEL: f1:
23; CHECK:       // %bb.0:
24; CHECK-NEXT:    {
25; CHECK-NEXT:     r0 = ##-1437226411
26; CHECK-NEXT:    }
27; CHECK-NEXT:    {
28; CHECK-NEXT:     v0 = vsplat(r0)
29; CHECK-NEXT:     jumpr r31
30; CHECK-NEXT:    }
31  %v0 = insertelement <64 x i16> undef, i16 43605, i32 0
32  %v1 = shufflevector <64 x i16> %v0, <64 x i16> undef, <64 x i32> zeroinitializer
33  ret <64 x i16> %v1
34}
35
36; Splat immediate, 32 bit, v60
37define <32 x i32> @f2() #0 {
38; CHECK-LABEL: f2:
39; CHECK:       // %bb.0:
40; CHECK-NEXT:    {
41; CHECK-NEXT:     r0 = ##134744072
42; CHECK-NEXT:    }
43; CHECK-NEXT:    {
44; CHECK-NEXT:     v0 = vsplat(r0)
45; CHECK-NEXT:     jumpr r31
46; CHECK-NEXT:    }
47  %v0 = insertelement <32 x i32> undef, i32 134744072, i32 0
48  %v1 = shufflevector <32 x i32> %v0, <32 x i32> undef, <32 x i32> zeroinitializer
49  ret <32 x i32> %v1
50}
51
52; Splat immediate, 8-bit, v62+
53define <128 x i8> @f3() #1 {
54; CHECK-LABEL: f3:
55; CHECK:       // %bb.0:
56; CHECK-NEXT:    {
57; CHECK-NEXT:     r0 = #127
58; CHECK-NEXT:    }
59; CHECK-NEXT:    {
60; CHECK-NEXT:     v0.b = vsplat(r0)
61; CHECK-NEXT:     jumpr r31
62; CHECK-NEXT:    }
63  %v0 = insertelement <128 x i8> undef, i8 127, i32 0
64  %v1 = shufflevector <128 x i8> %v0, <128 x i8> undef, <128 x i32> zeroinitializer
65  ret <128 x i8> %v1
66}
67
68; Splat immediate, 16 bit, v62+
69define <64 x i16> @f4() #1 {
70; CHECK-LABEL: f4:
71; CHECK:       // %bb.0:
72; CHECK-NEXT:    {
73; CHECK-NEXT:     r0 = #-21931
74; CHECK-NEXT:    }
75; CHECK-NEXT:    {
76; CHECK-NEXT:     v0.h = vsplat(r0)
77; CHECK-NEXT:     jumpr r31
78; CHECK-NEXT:    }
79  %v0 = insertelement <64 x i16> undef, i16 43605, i32 0
80  %v1 = shufflevector <64 x i16> %v0, <64 x i16> undef, <64 x i32> zeroinitializer
81  ret <64 x i16> %v1
82}
83
84; Splat immediate, 32 bit, v62+
85define <32 x i32> @f5() #1 {
86; CHECK-LABEL: f5:
87; CHECK:       // %bb.0:
88; CHECK-NEXT:    {
89; CHECK-NEXT:     r0 = ##134744072
90; CHECK-NEXT:    }
91; CHECK-NEXT:    {
92; CHECK-NEXT:     v0 = vsplat(r0)
93; CHECK-NEXT:     jumpr r31
94; CHECK-NEXT:    }
95  %v0 = insertelement <32 x i32> undef, i32 134744072, i32 0
96  %v1 = shufflevector <32 x i32> %v0, <32 x i32> undef, <32 x i32> zeroinitializer
97  ret <32 x i32> %v1
98}
99
100; Splat register, 8-bit, v60
101define <128 x i8> @f6(i8 %a0) #0 {
102; CHECK-LABEL: f6:
103; CHECK:       // %bb.0:
104; CHECK-NEXT:    {
105; CHECK-NEXT:     r0 = vsplatb(r0)
106; CHECK-NEXT:    }
107; CHECK-NEXT:    {
108; CHECK-NEXT:     v0 = vsplat(r0)
109; CHECK-NEXT:     jumpr r31
110; CHECK-NEXT:    }
111  %v0 = insertelement <128 x i8> undef, i8 %a0, i32 0
112  %v1 = shufflevector <128 x i8> %v0, <128 x i8> undef, <128 x i32> zeroinitializer
113  ret <128 x i8> %v1
114}
115
116; Splat register, 16 bit, v60
117define <64 x i16> @f7(i16 %a0) #0 {
118; CHECK-LABEL: f7:
119; CHECK:       // %bb.0:
120; CHECK-NEXT:    {
121; CHECK-NEXT:     r0 = combine(r0.l,r0.l)
122; CHECK-NEXT:    }
123; CHECK-NEXT:    {
124; CHECK-NEXT:     v0 = vsplat(r0)
125; CHECK-NEXT:     jumpr r31
126; CHECK-NEXT:    }
127  %v0 = insertelement <64 x i16> undef, i16 %a0, i32 0
128  %v1 = shufflevector <64 x i16> %v0, <64 x i16> undef, <64 x i32> zeroinitializer
129  ret <64 x i16> %v1
130}
131
132; Splat register, 32 bit, v60
133define <32 x i32> @f8(i32 %a0) #0 {
134; CHECK-LABEL: f8:
135; CHECK:       // %bb.0:
136; CHECK-NEXT:    {
137; CHECK-NEXT:     v0 = vsplat(r0)
138; CHECK-NEXT:     jumpr r31
139; CHECK-NEXT:    }
140  %v0 = insertelement <32 x i32> undef, i32 %a0, i32 0
141  %v1 = shufflevector <32 x i32> %v0, <32 x i32> undef, <32 x i32> zeroinitializer
142  ret <32 x i32> %v1
143}
144
145; Splat register, 8-bit, v62+
146define <128 x i8> @f9(i8 %a0) #1 {
147; CHECK-LABEL: f9:
148; CHECK:       // %bb.0:
149; CHECK-NEXT:    {
150; CHECK-NEXT:     v0.b = vsplat(r0)
151; CHECK-NEXT:     jumpr r31
152; CHECK-NEXT:    }
153  %v0 = insertelement <128 x i8> undef, i8 %a0, i32 0
154  %v1 = shufflevector <128 x i8> %v0, <128 x i8> undef, <128 x i32> zeroinitializer
155  ret <128 x i8> %v1
156}
157
158; Splat register, 16 bit, v62+
159define <64 x i16> @f10(i16 %a0) #1 {
160; CHECK-LABEL: f10:
161; CHECK:       // %bb.0:
162; CHECK-NEXT:    {
163; CHECK-NEXT:     v0.h = vsplat(r0)
164; CHECK-NEXT:     jumpr r31
165; CHECK-NEXT:    }
166  %v0 = insertelement <64 x i16> undef, i16 %a0, i32 0
167  %v1 = shufflevector <64 x i16> %v0, <64 x i16> undef, <64 x i32> zeroinitializer
168  ret <64 x i16> %v1
169}
170
171; Splat register, 32 bit, v62+
172define <32 x i32> @f11(i32 %a0) #1 {
173; CHECK-LABEL: f11:
174; CHECK:       // %bb.0:
175; CHECK-NEXT:    {
176; CHECK-NEXT:     v0 = vsplat(r0)
177; CHECK-NEXT:     jumpr r31
178; CHECK-NEXT:    }
179  %v0 = insertelement <32 x i32> undef, i32 %a0, i32 0
180  %v1 = shufflevector <32 x i32> %v0, <32 x i32> undef, <32 x i32> zeroinitializer
181  ret <32 x i32> %v1
182}
183
184; Splat immediate, 8-bit, v60, pair
185define <256 x i8> @f12() #0 {
186; CHECK-LABEL: f12:
187; CHECK:       // %bb.0:
188; CHECK-NEXT:    {
189; CHECK-NEXT:     r0 = ##2139062143
190; CHECK-NEXT:    }
191; CHECK-NEXT:    {
192; CHECK-NEXT:     v1 = vsplat(r0)
193; CHECK-NEXT:    }
194; CHECK-NEXT:    {
195; CHECK-NEXT:     v0 = v1
196; CHECK-NEXT:     jumpr r31
197; CHECK-NEXT:    }
198  %v0 = insertelement <256 x i8> undef, i8 127, i32 0
199  %v1 = shufflevector <256 x i8> %v0, <256 x i8> undef, <256 x i32> zeroinitializer
200  ret <256 x i8> %v1
201}
202
203; Splat immediate, 16 bit, v60, pair
204define <128 x i16> @f13() #0 {
205; CHECK-LABEL: f13:
206; CHECK:       // %bb.0:
207; CHECK-NEXT:    {
208; CHECK-NEXT:     r0 = ##-1437226411
209; CHECK-NEXT:    }
210; CHECK-NEXT:    {
211; CHECK-NEXT:     v1 = vsplat(r0)
212; CHECK-NEXT:    }
213; CHECK-NEXT:    {
214; CHECK-NEXT:     v0 = v1
215; CHECK-NEXT:     jumpr r31
216; CHECK-NEXT:    }
217  %v0 = insertelement <128 x i16> undef, i16 43605, i32 0
218  %v1 = shufflevector <128 x i16> %v0, <128 x i16> undef, <128 x i32> zeroinitializer
219  ret <128 x i16> %v1
220}
221
222; Splat immediate, 32 bit, v60, pair
223define <64 x i32> @f14() #0 {
224; CHECK-LABEL: f14:
225; CHECK:       // %bb.0:
226; CHECK-NEXT:    {
227; CHECK-NEXT:     r0 = ##134744072
228; CHECK-NEXT:    }
229; CHECK-NEXT:    {
230; CHECK-NEXT:     v1 = vsplat(r0)
231; CHECK-NEXT:    }
232; CHECK-NEXT:    {
233; CHECK-NEXT:     v0 = v1
234; CHECK-NEXT:     jumpr r31
235; CHECK-NEXT:    }
236  %v0 = insertelement <64 x i32> undef, i32 134744072, i32 0
237  %v1 = shufflevector <64 x i32> %v0, <64 x i32> undef, <64 x i32> zeroinitializer
238  ret <64 x i32> %v1
239}
240
241; Splat immediate, 8-bit, v62+, pair
242define <256 x i8> @f15() #1 {
243; CHECK-LABEL: f15:
244; CHECK:       // %bb.0:
245; CHECK-NEXT:    {
246; CHECK-NEXT:     r0 = #127
247; CHECK-NEXT:    }
248; CHECK-NEXT:    {
249; CHECK-NEXT:     v1.b = vsplat(r0)
250; CHECK-NEXT:    }
251; CHECK-NEXT:    {
252; CHECK-NEXT:     v0 = v1
253; CHECK-NEXT:     jumpr r31
254; CHECK-NEXT:    }
255  %v0 = insertelement <256 x i8> undef, i8 127, i32 0
256  %v1 = shufflevector <256 x i8> %v0, <256 x i8> undef, <256 x i32> zeroinitializer
257  ret <256 x i8> %v1
258}
259
260; Splat immediate, 16 bit, v62+, pair
261define <128 x i16> @f16() #1 {
262; CHECK-LABEL: f16:
263; CHECK:       // %bb.0:
264; CHECK-NEXT:    {
265; CHECK-NEXT:     r0 = #-21931
266; CHECK-NEXT:    }
267; CHECK-NEXT:    {
268; CHECK-NEXT:     v1.h = vsplat(r0)
269; CHECK-NEXT:    }
270; CHECK-NEXT:    {
271; CHECK-NEXT:     v0 = v1
272; CHECK-NEXT:     jumpr r31
273; CHECK-NEXT:    }
274  %v0 = insertelement <128 x i16> undef, i16 43605, i32 0
275  %v1 = shufflevector <128 x i16> %v0, <128 x i16> undef, <128 x i32> zeroinitializer
276  ret <128 x i16> %v1
277}
278
279; Splat immediate, 32 bit, v62+, pair
280define <64 x i32> @f17() #1 {
281; CHECK-LABEL: f17:
282; CHECK:       // %bb.0:
283; CHECK-NEXT:    {
284; CHECK-NEXT:     r0 = ##134744072
285; CHECK-NEXT:    }
286; CHECK-NEXT:    {
287; CHECK-NEXT:     v1 = vsplat(r0)
288; CHECK-NEXT:    }
289; CHECK-NEXT:    {
290; CHECK-NEXT:     v0 = v1
291; CHECK-NEXT:     jumpr r31
292; CHECK-NEXT:    }
293  %v0 = insertelement <64 x i32> undef, i32 134744072, i32 0
294  %v1 = shufflevector <64 x i32> %v0, <64 x i32> undef, <64 x i32> zeroinitializer
295  ret <64 x i32> %v1
296}
297
298; Splat register, 8-bit, v60, pair
299define <256 x i8> @f18(i8 %a0) #0 {
300; CHECK-LABEL: f18:
301; CHECK:       // %bb.0:
302; CHECK-NEXT:    {
303; CHECK-NEXT:     r0 = vsplatb(r0)
304; CHECK-NEXT:    }
305; CHECK-NEXT:    {
306; CHECK-NEXT:     v1 = vsplat(r0)
307; CHECK-NEXT:    }
308; CHECK-NEXT:    {
309; CHECK-NEXT:     v0 = v1
310; CHECK-NEXT:     jumpr r31
311; CHECK-NEXT:    }
312  %v0 = insertelement <256 x i8> undef, i8 %a0, i32 0
313  %v1 = shufflevector <256 x i8> %v0, <256 x i8> undef, <256 x i32> zeroinitializer
314  ret <256 x i8> %v1
315}
316
317; Splat register, 16 bit, v60, pair
318define <128 x i16> @f19(i16 %a0) #0 {
319; CHECK-LABEL: f19:
320; CHECK:       // %bb.0:
321; CHECK-NEXT:    {
322; CHECK-NEXT:     r0 = combine(r0.l,r0.l)
323; CHECK-NEXT:    }
324; CHECK-NEXT:    {
325; CHECK-NEXT:     v1 = vsplat(r0)
326; CHECK-NEXT:    }
327; CHECK-NEXT:    {
328; CHECK-NEXT:     v0 = v1
329; CHECK-NEXT:     jumpr r31
330; CHECK-NEXT:    }
331  %v0 = insertelement <128 x i16> undef, i16 %a0, i32 0
332  %v1 = shufflevector <128 x i16> %v0, <128 x i16> undef, <128 x i32> zeroinitializer
333  ret <128 x i16> %v1
334}
335
336; Splat register, 32 bit, v60, pair
337define <64 x i32> @f20(i32 %a0) #0 {
338; CHECK-LABEL: f20:
339; CHECK:       // %bb.0:
340; CHECK-NEXT:    {
341; CHECK-NEXT:     v1 = vsplat(r0)
342; CHECK-NEXT:    }
343; CHECK-NEXT:    {
344; CHECK-NEXT:     v0 = v1
345; CHECK-NEXT:     jumpr r31
346; CHECK-NEXT:    }
347  %v0 = insertelement <64 x i32> undef, i32 %a0, i32 0
348  %v1 = shufflevector <64 x i32> %v0, <64 x i32> undef, <64 x i32> zeroinitializer
349  ret <64 x i32> %v1
350}
351
352; Splat register, 8-bit, v62+, pair
353define <256 x i8> @f21(i8 %a0) #1 {
354; CHECK-LABEL: f21:
355; CHECK:       // %bb.0:
356; CHECK-NEXT:    {
357; CHECK-NEXT:     v1.b = vsplat(r0)
358; CHECK-NEXT:    }
359; CHECK-NEXT:    {
360; CHECK-NEXT:     v0 = v1
361; CHECK-NEXT:     jumpr r31
362; CHECK-NEXT:    }
363  %v0 = insertelement <256 x i8> undef, i8 %a0, i32 0
364  %v1 = shufflevector <256 x i8> %v0, <256 x i8> undef, <256 x i32> zeroinitializer
365  ret <256 x i8> %v1
366}
367
368; Splat register, 16 bit, v62+, pair
369define <128 x i16> @f22(i16 %a0) #1 {
370; CHECK-LABEL: f22:
371; CHECK:       // %bb.0:
372; CHECK-NEXT:    {
373; CHECK-NEXT:     v1.h = vsplat(r0)
374; CHECK-NEXT:    }
375; CHECK-NEXT:    {
376; CHECK-NEXT:     v0 = v1
377; CHECK-NEXT:     jumpr r31
378; CHECK-NEXT:    }
379  %v0 = insertelement <128 x i16> undef, i16 %a0, i32 0
380  %v1 = shufflevector <128 x i16> %v0, <128 x i16> undef, <128 x i32> zeroinitializer
381  ret <128 x i16> %v1
382}
383
384; Splat register, 32 bit, v62+, pair
385define <64 x i32> @f23(i32 %a0) #1 {
386; CHECK-LABEL: f23:
387; CHECK:       // %bb.0:
388; CHECK-NEXT:    {
389; CHECK-NEXT:     v1 = vsplat(r0)
390; CHECK-NEXT:    }
391; CHECK-NEXT:    {
392; CHECK-NEXT:     v0 = v1
393; CHECK-NEXT:     jumpr r31
394; CHECK-NEXT:    }
395  %v0 = insertelement <64 x i32> undef, i32 %a0, i32 0
396  %v1 = shufflevector <64 x i32> %v0, <64 x i32> undef, <64 x i32> zeroinitializer
397  ret <64 x i32> %v1
398}
399
400attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" }
401attributes #1 = { nounwind readnone "target-cpu"="hexagonv62" "target-features"="+hvxv62,+hvx-length128b" }
402