1; RUN: llc -march=hexagon -hexagon-initial-cfg-cleanup=0 -hexagon-instsimplify=0 < %s | FileCheck %s
2
3; Check for successful compilation.
4; CHECK: r{{[0-9]+}} = insert(r{{[0-9]+}},#1,#31)
5
6; This cannot be a .mir test, because the failure depends on ordering of
7; virtual registers, and the .mir loader renumbers them in a way that hides
8; the problem.
9
10target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
11target triple = "hexagon"
12
13; Function Attrs: nounwind
14define void @f0() #0 align 2 {
15b0:
16  br label %b1
17
18b1:                                               ; preds = %b3, %b0
19  %v0 = phi i64 [ 0, %b0 ], [ %v6, %b3 ]
20  br i1 undef, label %b2, label %b3
21
22b2:                                               ; preds = %b1
23  br label %b3
24
25b3:                                               ; preds = %b2, %b1
26  %v1 = phi i64 [ undef, %b2 ], [ %v0, %b1 ]
27  %v2 = and i64 %v1, 1
28  %v3 = trunc i64 %v2 to i32
29  %v4 = tail call i32 @llvm.hexagon.C2.mux(i32 %v3, i32 undef, i32 undef)
30  %v5 = trunc i32 %v4 to i8
31  store i8 %v5, i8* undef, align 1
32  %v6 = lshr i64 %v1, 1
33  br label %b1
34}
35
36; Function Attrs: nounwind readnone
37declare i32 @llvm.hexagon.C2.mux(i32, i32, i32) #1
38
39attributes #0 = { nounwind "target-cpu"="hexagonv60" }
40attributes #1 = { nounwind readnone }
41