1; RUN: llc -march=hexagon -verify-machineinstrs=true < %s | FileCheck %s
2; Testing for these 5 variants of circular store:
3;   Q6_circ_store_update_B(inputLR, pDelay, -1, nConvLength, 4);
4;   Q6_circ_store_update_D(inputLR, pDelay, -1, nConvLength, 4);
5;   Q6_circ_store_update_HL(inputLR, pDelay, -1, nConvLength, 4);
6;   Q6_circ_store_update_HH(inputLR, pDelay, -1, nConvLength, 4);
7;   Q6_circ_store_update_W(inputLR, pDelay, -1, nConvLength, 4);
8; producing these
9;   memb(r1++#-1:circ(m0)) = r3
10;   memd(r1++#-8:circ(m0)) = r1:0
11;   memh(r1++#-2:circ(m0)) = r3
12;   memh(r1++#-2:circ(m0)) = r3.h
13;   memw(r1++#-4:circ(m0)) = r0
14
15target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32"
16target triple = "hexagon"
17
18define zeroext i8 @foo1(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind {
19entry:
20  %conv = zext i16 %filtMemLen to i32
21  %shr2 = lshr i32 %conv, 1
22  %idxprom = sext i16 %filtMemIndex to i32
23  %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom
24  %0 = bitcast i16* %arrayidx to i8*
25  %or = or i32 %shr2, 33554432
26; CHECK: memb(r{{[0-9]+}}++#-1:circ(m{{[0-1]}}))
27  %1 = tail call i8* @llvm.hexagon.circ.stb(i8* %0, i32 0, i32 %or, i32 -1)
28  ret i8 0
29}
30
31declare i8* @llvm.hexagon.circ.stb(i8*, i32, i32, i32) nounwind
32
33define i64 @foo2(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind {
34entry:
35  %conv = zext i16 %filtMemLen to i32
36  %shr1 = lshr i32 %conv, 1
37  %idxprom = sext i16 %filtMemIndex to i32
38  %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom
39  %0 = bitcast i16* %arrayidx to i8*
40  %shl = shl nuw nsw i32 %shr1, 3
41  %or = or i32 %shl, 83886080
42; CHECK: memd(r{{[0-9]+}}++#-8:circ(m{{[0-1]}}))
43  %1 = tail call i8* @llvm.hexagon.circ.std(i8* %0, i64 undef, i32 %or, i32 -8)
44  ret i64 0
45}
46
47declare i8* @llvm.hexagon.circ.std(i8*, i64, i32, i32) nounwind
48
49define signext i16 @foo3(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind {
50entry:
51  %conv = zext i16 %filtMemLen to i32
52  %shr2 = and i32 %conv, 65534
53  %idxprom = sext i16 %filtMemIndex to i32
54  %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom
55  %0 = bitcast i16* %arrayidx to i8*
56  %or = or i32 %shr2, 50331648
57; CHECK: memh(r{{[0-9]+}}++#-2:circ(m{{[0-1]}}))
58  %1 = tail call i8* @llvm.hexagon.circ.sth(i8* %0, i32 0, i32 %or, i32 -2)
59  ret i16 0
60}
61
62declare i8* @llvm.hexagon.circ.sth(i8*, i32, i32, i32) nounwind
63
64define signext i16 @foo5(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind {
65entry:
66  %conv = zext i16 %filtMemLen to i32
67  %shr2 = and i32 %conv, 65534
68  %idxprom = sext i16 %filtMemIndex to i32
69  %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom
70  %0 = bitcast i16* %arrayidx to i8*
71  %or = or i32 %shr2, 50331648
72; CHECK: memh(r{{[0-9]+}}++#-2:circ(m{{[0-1]}})) = r{{[0-9]*}}.h
73  %1 = tail call i8* @llvm.hexagon.circ.sthhi(i8* %0, i32 0, i32 %or, i32 -2)
74  ret i16 0
75}
76
77declare i8* @llvm.hexagon.circ.sthhi(i8*, i32, i32, i32) nounwind
78
79define i32 @foo6(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind {
80entry:
81  %conv = zext i16 %filtMemLen to i32
82  %shr1 = lshr i32 %conv, 1
83  %idxprom = sext i16 %filtMemIndex to i32
84  %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom
85  %0 = bitcast i16* %arrayidx to i8*
86  %shl = shl nuw nsw i32 %shr1, 2
87  %or = or i32 %shl, 67108864
88; CHECK: memw(r{{[0-9]+}}++#-4:circ(m{{[0-1]}}))
89  %1 = tail call i8* @llvm.hexagon.circ.stw(i8* %0, i32 undef, i32 %or, i32 -4)
90  ret i32 0
91}
92
93declare i8* @llvm.hexagon.circ.stw(i8*, i32, i32, i32) nounwind
94
95!0 = !{!"omnipotent char", !1}
96!1 = !{!"Simple C/C++ TBAA"}
97!2 = !{!"short", !0}
98!3 = !{!"int", !0}
99