1; RUN: llc -march=hexagon -O3 < %s | FileCheck %s
2
3target triple = "hexagon"
4
5; CHECK-LABEL: f0:
6; CHECK: p{{[0-9]+}} = sfcmp.ge(r{{[0-9]+}},r{{[0-9]+}})
7; CHECK: p{{[0-9]+}} = sfcmp.gt(r{{[0-9]+}},r{{[0-9]+}})
8define i32 @f0(float* nocapture %a0) #0 {
9b0:
10  %v0 = load float, float* %a0, align 4, !tbaa !0
11  %v1 = fcmp olt float %v0, 6.000000e+01
12  br i1 %v1, label %b1, label %b2
13
14b1:                                               ; preds = %b0
15  %v2 = getelementptr inbounds float, float* %a0, i32 1
16  %v3 = load float, float* %v2, align 4, !tbaa !0
17  %v4 = fcmp ogt float %v3, 0x3FECCCCCC0000000
18  br label %b2
19
20b2:                                               ; preds = %b1, %b0
21  %v5 = phi i1 [ false, %b0 ], [ %v4, %b1 ]
22  %v6 = zext i1 %v5 to i32
23  ret i32 %v6
24}
25
26; CHECK-LABEL: f1:
27; CHECK: p{{[0-9]+}} = sfcmp.eq(r{{[0-9]+}},r{{[0-9]+}})
28define i32 @f1(float* nocapture %a0) #0 {
29b0:
30  %v0 = load float, float* %a0, align 4, !tbaa !0
31  %v1 = fcmp oeq float %v0, 6.000000e+01
32  %v2 = zext i1 %v1 to i32
33  ret i32 %v2
34}
35
36; CHECK-LABEL: f2:
37; CHECK: p{{[0-9]+}} = dfcmp.ge(r{{[0-9]+}}:{{[0-9]+}},r{{[0-9]+}}:{{[0-9]+}})
38; CHECK: p{{[0-9]+}} = dfcmp.gt(r{{[0-9]+}}:{{[0-9]+}},r{{[0-9]+}}:{{[0-9]+}})
39define i32 @f2(double* nocapture %a0) #0 {
40b0:
41  %v0 = load double, double* %a0, align 8, !tbaa !4
42  %v1 = fcmp olt double %v0, 6.000000e+01
43  br i1 %v1, label %b1, label %b2
44
45b1:                                               ; preds = %b0
46  %v2 = getelementptr inbounds double, double* %a0, i32 1
47  %v3 = load double, double* %v2, align 8, !tbaa !4
48  %v4 = fcmp ogt double %v3, 0x3FECCCCCC0000000
49  br label %b2
50
51b2:                                               ; preds = %b1, %b0
52  %v5 = phi i1 [ false, %b0 ], [ %v4, %b1 ]
53  %v6 = zext i1 %v5 to i32
54  ret i32 %v6
55}
56
57define i32 @f3(double* nocapture %a0) #0 {
58b0:
59  %v0 = load double, double* %a0, align 8, !tbaa !4
60  %v1 = fcmp oeq double %v0, 6.000000e+01
61  %v2 = zext i1 %v1 to i32
62  ret i32 %v2
63}
64
65attributes #0 = { nounwind readonly "target-cpu"="hexagonv55" "no-nans-fp-math"="true" }
66
67!0 = !{!1, !1, i64 0}
68!1 = !{!"float", !2}
69!2 = !{!"omnipotent char", !3}
70!3 = !{!"Simple C/C++ TBAA"}
71!4 = !{!5, !5, i64 0}
72!5 = !{!"double", !2}
73