1; Run -O2 to make sure that all the usual optimizations do happen before
2; the Hexagon loop idiom recognition runs. This is to check that we still
3; get this opportunity regardless of what happens before.
4
5; RUN: opt -O2 -march=hexagon -S < %s | FileCheck %s
6; RUN: opt -aa-pipeline=default -passes='default<O2>' -march=hexagon -S < %s | FileCheck %s
7
8target triple = "hexagon"
9target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
10
11; CHECK-LABEL: define zeroext i16 @pmpy_mod_lsr
12; There need to be two pmpy instructions.
13; CHECK: call i64 @llvm.hexagon.M4.pmpyw
14; CHECK: call i64 @llvm.hexagon.M4.pmpyw
15
16define zeroext i16 @pmpy_mod_lsr(i8 zeroext %a0, i16 zeroext %a1) #0 {
17b2:
18  br label %b3
19
20b3:                                               ; preds = %b44, %b2
21  %v4 = phi i8 [ %a0, %b2 ], [ %v19, %b44 ]
22  %v5 = phi i16 [ %a1, %b2 ], [ %v43, %b44 ]
23  %v6 = phi i8 [ 0, %b2 ], [ %v45, %b44 ]
24  %v7 = zext i8 %v6 to i32
25  %v8 = icmp slt i32 %v7, 8
26  br i1 %v8, label %b9, label %b46
27
28b9:                                               ; preds = %b3
29  %v10 = zext i8 %v4 to i32
30  %v11 = and i32 %v10, 1
31  %v12 = trunc i16 %v5 to i8
32  %v13 = zext i8 %v12 to i32
33  %v14 = and i32 %v13, 1
34  %v15 = xor i32 %v11, %v14
35  %v16 = trunc i32 %v15 to i8
36  %v17 = zext i8 %v4 to i32
37  %v18 = ashr i32 %v17, 1
38  %v19 = trunc i32 %v18 to i8
39  %v20 = zext i8 %v16 to i32
40  %v21 = icmp eq i32 %v20, 1
41  br i1 %v21, label %b22, label %b26
42
43b22:                                              ; preds = %b9
44  %v23 = zext i16 %v5 to i32
45  %v24 = xor i32 %v23, 16386
46  %v25 = trunc i32 %v24 to i16
47  br label %b27
48
49b26:                                              ; preds = %b9
50  br label %b27
51
52b27:                                              ; preds = %b26, %b22
53  %v28 = phi i16 [ %v25, %b22 ], [ %v5, %b26 ]
54  %v29 = phi i8 [ 1, %b22 ], [ 0, %b26 ]
55  %v30 = zext i16 %v28 to i32
56  %v31 = ashr i32 %v30, 1
57  %v32 = trunc i32 %v31 to i16
58  %v33 = icmp ne i8 %v29, 0
59  br i1 %v33, label %b34, label %b38
60
61b34:                                              ; preds = %b27
62  %v35 = zext i16 %v32 to i32
63  %v36 = or i32 %v35, 32768
64  %v37 = trunc i32 %v36 to i16
65  br label %b42
66
67b38:                                              ; preds = %b27
68  %v39 = zext i16 %v32 to i32
69  %v40 = and i32 %v39, 32767
70  %v41 = trunc i32 %v40 to i16
71  br label %b42
72
73b42:                                              ; preds = %b38, %b34
74  %v43 = phi i16 [ %v37, %b34 ], [ %v41, %b38 ]
75  br label %b44
76
77b44:                                              ; preds = %b42
78  %v45 = add i8 %v6, 1
79  br label %b3
80
81b46:                                              ; preds = %b3
82  ret i16 %v5
83}
84
85attributes #0 = { noinline nounwind "target-cpu"="hexagonv5" "target-features"="-hvx,-long-calls" }
86