1; RUN: llc -march=hexagon -enable-pipeliner -hexagon-initial-cfg-cleanup=0 < %s -pipeliner-experimental-cg=true | FileCheck %s
2
3; Test that the code that changes the dependences does not allow
4; a load with a negative offset to be overlapped with the post
5; increment store that generates the base register.
6
7; CHECK: loop0(.LBB0_[[LOOP:.]],
8; CHECK: .LBB0_[[LOOP]]:
9; CHECK: = mem{{u?}}b([[REG:(r[0-9])+]]+#-1)
10; CHECK-NOT: memb([[REG]]{{\+?}}#0) =
11; CHECK: }
12; CHECK: }{{[ \t]*}}:endloop0
13
14@g0 = external global [1000000 x i8], align 8
15
16; Function Attrs: nounwind
17define void @f0(i32 %a0, [1000 x i8]* %a1, [1000 x i8]* %a2) #0 {
18b0:
19  br i1 undef, label %b1, label %b7
20
21b1:                                               ; preds = %b0
22  br i1 undef, label %b2, label %b6
23
24b2:                                               ; preds = %b5, %b1
25  br i1 undef, label %b3, label %b5
26
27b3:                                               ; preds = %b3, %b2
28  %v0 = phi i32 [ %v17, %b3 ], [ 1, %b2 ]
29  %v1 = phi i32 [ %v16, %b3 ], [ 0, %b2 ]
30  %v2 = add nsw i32 %v0, -1
31  %v3 = getelementptr inbounds [1000 x i8], [1000 x i8]* %a1, i32 undef, i32 %v2
32  %v4 = load i8, i8* %v3, align 1, !tbaa !0
33  %v5 = zext i8 %v4 to i32
34  %v6 = getelementptr inbounds [1000000 x i8], [1000000 x i8]* @g0, i32 0, i32 %v1
35  %v7 = load i8, i8* %v6, align 1, !tbaa !0
36  %v8 = sext i8 %v7 to i32
37  %v9 = getelementptr inbounds [1000 x i8], [1000 x i8]* %a2, i32 undef, i32 %v0
38  %v10 = load i8, i8* %v9, align 1, !tbaa !0
39  %v11 = sext i8 %v10 to i32
40  %v12 = mul nsw i32 %v11, %v8
41  %v13 = add nsw i32 %v12, %v5
42  %v14 = trunc i32 %v13 to i8
43  %v15 = getelementptr inbounds [1000 x i8], [1000 x i8]* %a1, i32 undef, i32 %v0
44  store i8 %v14, i8* %v15, align 1, !tbaa !0
45  %v16 = add nsw i32 %v1, 1
46  %v17 = add nsw i32 %v0, 1
47  %v18 = icmp eq i32 %v17, %a0
48  br i1 %v18, label %b4, label %b3
49
50b4:                                               ; preds = %b3
51  br label %b5
52
53b5:                                               ; preds = %b4, %b2
54  br i1 undef, label %b6, label %b2
55
56b6:                                               ; preds = %b5, %b1
57  unreachable
58
59b7:                                               ; preds = %b0
60  ret void
61}
62
63attributes #0 = { nounwind "target-cpu"="hexagonv55" }
64
65!0 = !{!1, !1, i64 0}
66!1 = !{!"omnipotent char", !2, i64 0}
67!2 = !{!"Simple C/C++ TBAA"}
68