1; RUN: llc -march=hexagon -O2 < %s
2; REQUIRES: asserts
3
4; Function Attrs: noinline nounwind ssp
5define fastcc void @f0() #0 {
6b0:
7  %v0 = add i32 0, 39
8  %v1 = and i32 %v0, -8
9  br i1 undef, label %b1, label %b2
10
11b1:                                               ; preds = %b1, %b0
12  %v2 = phi i32 [ %v10, %b1 ], [ undef, %b0 ]
13  %v3 = phi i8* [ %v7, %b1 ], [ undef, %b0 ]
14  %v4 = ptrtoint i8* %v3 to i32
15  %v5 = add i32 %v4, %v1
16  %v6 = bitcast i8* %v3 to i32*
17  store i32 %v5, i32* %v6, align 4
18  %v7 = getelementptr inbounds i8, i8* %v3, i32 %v1
19  %v8 = getelementptr inbounds i8, i8* %v3, i32 0
20  %v9 = bitcast i8* %v8 to i32*
21  store i32 1111638594, i32* %v9, align 4
22  %v10 = add nsw i32 %v2, -1
23  %v11 = icmp sgt i32 %v10, 0
24  br i1 %v11, label %b1, label %b2
25
26b2:                                               ; preds = %b1, %b0
27  ret void
28}
29
30attributes #0 = { noinline nounwind ssp "target-cpu"="hexagonv55" }
31