1; RUN: llc -march=hexagon -enable-pipeliner -debug-only=pipeliner < %s -o - 2>&1 > /dev/null -pipeliner-experimental-cg=true | FileCheck %s
2; REQUIRES: asserts
3
4; Test that checks that we compute the correct ResMII for haar.
5
6; CHECK: MII = 4 MAX_II = 14 (rec=1, res=4)
7
8; Function Attrs: nounwind
9define void @f0(i16* noalias nocapture readonly %a0, i32 %a1, i32 %a2, i32 %a3, i8* noalias nocapture %a4, i32 %a5) #0 {
10b0:
11  %v0 = ashr i32 %a3, 2
12  %v1 = ashr i32 %a3, 1
13  %v2 = add i32 %v1, %v0
14  %v3 = icmp sgt i32 %a2, 0
15  br i1 %v3, label %b1, label %b8
16
17b1:                                               ; preds = %b0
18  %v4 = sdiv i32 %a1, 64
19  %v5 = icmp sgt i32 %a1, 63
20  br label %b2
21
22b2:                                               ; preds = %b6, %b1
23  %v6 = phi i32 [ 0, %b1 ], [ %v56, %b6 ]
24  %v7 = ashr exact i32 %v6, 1
25  %v8 = mul nsw i32 %v7, %a3
26  br i1 %v5, label %b3, label %b6
27
28b3:                                               ; preds = %b2
29  %v9 = add nsw i32 %v6, 1
30  %v10 = mul nsw i32 %v9, %a5
31  %v11 = mul nsw i32 %v6, %a5
32  %v12 = add i32 %v2, %v8
33  %v13 = add i32 %v8, %v0
34  %v14 = add i32 %v8, %v1
35  %v15 = getelementptr inbounds i8, i8* %a4, i32 %v10
36  %v16 = getelementptr inbounds i8, i8* %a4, i32 %v11
37  %v17 = getelementptr inbounds i16, i16* %a0, i32 %v12
38  %v18 = getelementptr inbounds i16, i16* %a0, i32 %v13
39  %v19 = getelementptr inbounds i16, i16* %a0, i32 %v14
40  %v20 = getelementptr inbounds i16, i16* %a0, i32 %v8
41  %v21 = bitcast i8* %v15 to <16 x i32>*
42  %v22 = bitcast i8* %v16 to <16 x i32>*
43  %v23 = bitcast i16* %v17 to <16 x i32>*
44  %v24 = bitcast i16* %v18 to <16 x i32>*
45  %v25 = bitcast i16* %v19 to <16 x i32>*
46  %v26 = bitcast i16* %v20 to <16 x i32>*
47  br label %b4
48
49b4:                                               ; preds = %b4, %b3
50  %v27 = phi i32 [ 0, %b3 ], [ %v54, %b4 ]
51  %v28 = phi <16 x i32>* [ %v26, %b3 ], [ %v34, %b4 ]
52  %v29 = phi <16 x i32>* [ %v25, %b3 ], [ %v36, %b4 ]
53  %v30 = phi <16 x i32>* [ %v24, %b3 ], [ %v38, %b4 ]
54  %v31 = phi <16 x i32>* [ %v23, %b3 ], [ %v40, %b4 ]
55  %v32 = phi <16 x i32>* [ %v21, %b3 ], [ %v53, %b4 ]
56  %v33 = phi <16 x i32>* [ %v22, %b3 ], [ %v52, %b4 ]
57  %v34 = getelementptr inbounds <16 x i32>, <16 x i32>* %v28, i32 1
58  %v35 = load <16 x i32>, <16 x i32>* %v28, align 64
59  %v36 = getelementptr inbounds <16 x i32>, <16 x i32>* %v29, i32 1
60  %v37 = load <16 x i32>, <16 x i32>* %v29, align 64
61  %v38 = getelementptr inbounds <16 x i32>, <16 x i32>* %v30, i32 1
62  %v39 = load <16 x i32>, <16 x i32>* %v30, align 64
63  %v40 = getelementptr inbounds <16 x i32>, <16 x i32>* %v31, i32 1
64  %v41 = load <16 x i32>, <16 x i32>* %v31, align 64
65  %v42 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> %v35, <16 x i32> %v37)
66  %v43 = tail call <16 x i32> @llvm.hexagon.V6.vsubh(<16 x i32> %v35, <16 x i32> %v37)
67  %v44 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> %v39, <16 x i32> %v41)
68  %v45 = tail call <16 x i32> @llvm.hexagon.V6.vsubh(<16 x i32> %v39, <16 x i32> %v41)
69  %v46 = tail call <16 x i32> @llvm.hexagon.V6.vavgh(<16 x i32> %v42, <16 x i32> %v44)
70  %v47 = tail call <16 x i32> @llvm.hexagon.V6.vnavgh(<16 x i32> %v42, <16 x i32> %v44)
71  %v48 = tail call <16 x i32> @llvm.hexagon.V6.vavgh(<16 x i32> %v43, <16 x i32> %v45)
72  %v49 = tail call <16 x i32> @llvm.hexagon.V6.vnavgh(<16 x i32> %v43, <16 x i32> %v45)
73  %v50 = tail call <16 x i32> @llvm.hexagon.V6.vsathub(<16 x i32> %v47, <16 x i32> %v46)
74  %v51 = tail call <16 x i32> @llvm.hexagon.V6.vsathub(<16 x i32> %v49, <16 x i32> %v48)
75  %v52 = getelementptr inbounds <16 x i32>, <16 x i32>* %v33, i32 1
76  store <16 x i32> %v50, <16 x i32>* %v33, align 64
77  %v53 = getelementptr inbounds <16 x i32>, <16 x i32>* %v32, i32 1
78  store <16 x i32> %v51, <16 x i32>* %v32, align 64
79  %v54 = add nsw i32 %v27, 1
80  %v55 = icmp slt i32 %v54, %v4
81  br i1 %v55, label %b4, label %b5
82
83b5:                                               ; preds = %b4
84  br label %b6
85
86b6:                                               ; preds = %b5, %b2
87  %v56 = add nsw i32 %v6, 2
88  %v57 = icmp slt i32 %v56, %a2
89  br i1 %v57, label %b2, label %b7
90
91b7:                                               ; preds = %b6
92  br label %b8
93
94b8:                                               ; preds = %b7, %b0
95  ret void
96}
97
98; Function Attrs: nounwind readnone
99declare <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32>, <16 x i32>) #1
100
101; Function Attrs: nounwind readnone
102declare <16 x i32> @llvm.hexagon.V6.vsubh(<16 x i32>, <16 x i32>) #1
103
104; Function Attrs: nounwind readnone
105declare <16 x i32> @llvm.hexagon.V6.vavgh(<16 x i32>, <16 x i32>) #1
106
107; Function Attrs: nounwind readnone
108declare <16 x i32> @llvm.hexagon.V6.vnavgh(<16 x i32>, <16 x i32>) #1
109
110; Function Attrs: nounwind readnone
111declare <16 x i32> @llvm.hexagon.V6.vsathub(<16 x i32>, <16 x i32>) #1
112
113attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
114attributes #1 = { nounwind readnone }
115