1; RUN: llc -march=hexagon -O3 < %s
2; REQUIRES: asserts
3
4; Test that we don't assert because the compiler generates the wrong register
5; class for the vector spill code in 128B mode.
6
7define void @f0(i32 %a0) #0 {
8b0:
9  %v0 = tail call <32 x i32> @llvm.hexagon.V6.lvsplatw.128B(i32 16843009)
10  %v1 = tail call <32 x i32> @llvm.hexagon.V6.vshuffh.128B(<32 x i32> undef)
11  %v2 = tail call <32 x i32> @llvm.hexagon.V6.vshuffh.128B(<32 x i32> zeroinitializer)
12  %v3 = sdiv i32 %a0, 128
13  %v4 = icmp sgt i32 %a0, 127
14  br i1 %v4, label %b1, label %b2
15
16b1:                                               ; preds = %b1, %b0
17  %v5 = phi i32 [ %v77, %b1 ], [ 0, %b0 ]
18  %v6 = phi <32 x i32>* [ undef, %b1 ], [ undef, %b0 ]
19  %v7 = tail call <32 x i32> @llvm.hexagon.V6.vabsdiffub.128B(<32 x i32> undef, <32 x i32> undef)
20  %v8 = tail call <128 x i1> @llvm.hexagon.V6.vgtub.128B(<32 x i32> %v7, <32 x i32> zeroinitializer)
21  %v9 = tail call <32 x i32> @llvm.hexagon.V6.vaddbnq.128B(<128 x i1> %v8, <32 x i32> undef, <32 x i32> %v0)
22  %v10 = tail call <32 x i32> @llvm.hexagon.V6.valignbi.128B(<32 x i32> undef, <32 x i32> undef, i32 3)
23  %v11 = tail call <32 x i32> @llvm.hexagon.V6.vabsdiffub.128B(<32 x i32> zeroinitializer, <32 x i32> undef)
24  %v12 = tail call <32 x i32> @llvm.hexagon.V6.vabsdiffub.128B(<32 x i32> %v10, <32 x i32> undef)
25  %v13 = tail call <128 x i1> @llvm.hexagon.V6.vgtub.128B(<32 x i32> %v11, <32 x i32> zeroinitializer)
26  %v14 = tail call <128 x i1> @llvm.hexagon.V6.vgtub.128B(<32 x i32> %v12, <32 x i32> zeroinitializer)
27  %v15 = tail call <32 x i32> @llvm.hexagon.V6.vaddbnq.128B(<128 x i1> %v13, <32 x i32> %v9, <32 x i32> %v0)
28  %v16 = tail call <32 x i32> @llvm.hexagon.V6.vaddbnq.128B(<128 x i1> %v14, <32 x i32> %v15, <32 x i32> %v0)
29  %v17 = tail call <32 x i32> @llvm.hexagon.V6.vaddbnq.128B(<128 x i1> undef, <32 x i32> %v16, <32 x i32> %v0)
30  %v18 = tail call <32 x i32> @llvm.hexagon.V6.vaddbnq.128B(<128 x i1> undef, <32 x i32> %v17, <32 x i32> %v0)
31  %v19 = tail call <128 x i1> @llvm.hexagon.V6.vgtub.128B(<32 x i32> undef, <32 x i32> zeroinitializer)
32  %v20 = tail call <32 x i32> @llvm.hexagon.V6.vaddbnq.128B(<128 x i1> %v19, <32 x i32> %v18, <32 x i32> %v0)
33  %v21 = tail call <128 x i1> @llvm.hexagon.V6.vgtub.128B(<32 x i32> undef, <32 x i32> zeroinitializer)
34  %v22 = tail call <32 x i32> @llvm.hexagon.V6.vmux.128B(<128 x i1> undef, <32 x i32> undef, <32 x i32> undef)
35  %v23 = tail call <32 x i32> @llvm.hexagon.V6.vmux.128B(<128 x i1> %v21, <32 x i32> undef, <32 x i32> undef)
36  %v24 = tail call <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32> %v23, <32 x i32> %v22)
37  %v25 = tail call <64 x i32> @llvm.hexagon.V6.vmpabus.acc.128B(<64 x i32> zeroinitializer, <64 x i32> %v24, i32 16843009)
38  %v26 = tail call <32 x i32> @llvm.hexagon.V6.vaddbnq.128B(<128 x i1> undef, <32 x i32> %v20, <32 x i32> %v0)
39  %v27 = tail call <32 x i32> @llvm.hexagon.V6.vaddbnq.128B(<128 x i1> undef, <32 x i32> %v26, <32 x i32> %v0)
40  %v28 = tail call <32 x i32> @llvm.hexagon.V6.vaddbnq.128B(<128 x i1> undef, <32 x i32> %v27, <32 x i32> %v0)
41  %v29 = tail call <32 x i32> @llvm.hexagon.V6.vaddbnq.128B(<128 x i1> %v21, <32 x i32> %v28, <32 x i32> %v0)
42  %v30 = tail call <128 x i1> @llvm.hexagon.V6.vgtub.128B(<32 x i32> undef, <32 x i32> zeroinitializer)
43  %v31 = tail call <32 x i32> @llvm.hexagon.V6.vmux.128B(<128 x i1> undef, <32 x i32> undef, <32 x i32> zeroinitializer)
44  %v32 = tail call <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32> %v31, <32 x i32> undef)
45  %v33 = tail call <64 x i32> @llvm.hexagon.V6.vmpabus.acc.128B(<64 x i32> %v25, <64 x i32> %v32, i32 16843009)
46  %v34 = tail call <64 x i32> @llvm.hexagon.V6.vmpabus.acc.128B(<64 x i32> %v33, <64 x i32> undef, i32 16843009)
47  %v35 = tail call <32 x i32> @llvm.hexagon.V6.vaddbnq.128B(<128 x i1> undef, <32 x i32> %v29, <32 x i32> %v0)
48  %v36 = tail call <32 x i32> @llvm.hexagon.V6.vaddbnq.128B(<128 x i1> undef, <32 x i32> %v35, <32 x i32> %v0)
49  %v37 = tail call <32 x i32> @llvm.hexagon.V6.vaddbnq.128B(<128 x i1> undef, <32 x i32> %v36, <32 x i32> %v0)
50  %v38 = tail call <32 x i32> @llvm.hexagon.V6.vaddbnq.128B(<128 x i1> %v30, <32 x i32> %v37, <32 x i32> %v0)
51  %v39 = load <32 x i32>, <32 x i32>* null, align 128, !tbaa !0
52  %v40 = tail call <128 x i1> @llvm.hexagon.V6.vgtub.128B(<32 x i32> undef, <32 x i32> zeroinitializer)
53  %v41 = tail call <32 x i32> @llvm.hexagon.V6.vmux.128B(<128 x i1> %v40, <32 x i32> undef, <32 x i32> %v39)
54  %v42 = tail call <64 x i32> @llvm.hexagon.V6.vmpybus.acc.128B(<64 x i32> %v34, <32 x i32> %v41, i32 16843009)
55  %v43 = tail call <32 x i32> @llvm.hexagon.V6.vaddbnq.128B(<128 x i1> %v40, <32 x i32> %v38, <32 x i32> %v0)
56  %v44 = tail call <32 x i32> @llvm.hexagon.V6.vlalignbi.128B(<32 x i32> %v39, <32 x i32> undef, i32 1)
57  %v45 = tail call <32 x i32> @llvm.hexagon.V6.valignbi.128B(<32 x i32> undef, <32 x i32> %v39, i32 1)
58  %v46 = tail call <32 x i32> @llvm.hexagon.V6.valignbi.128B(<32 x i32> undef, <32 x i32> %v39, i32 2)
59  %v47 = tail call <32 x i32> @llvm.hexagon.V6.vabsdiffub.128B(<32 x i32> %v44, <32 x i32> undef)
60  %v48 = tail call <32 x i32> @llvm.hexagon.V6.vabsdiffub.128B(<32 x i32> %v45, <32 x i32> undef)
61  %v49 = tail call <32 x i32> @llvm.hexagon.V6.vabsdiffub.128B(<32 x i32> %v46, <32 x i32> undef)
62  %v50 = tail call <128 x i1> @llvm.hexagon.V6.vgtub.128B(<32 x i32> %v47, <32 x i32> zeroinitializer)
63  %v51 = tail call <128 x i1> @llvm.hexagon.V6.vgtub.128B(<32 x i32> %v48, <32 x i32> zeroinitializer)
64  %v52 = tail call <128 x i1> @llvm.hexagon.V6.vgtub.128B(<32 x i32> %v49, <32 x i32> zeroinitializer)
65  %v53 = tail call <32 x i32> @llvm.hexagon.V6.vmux.128B(<128 x i1> %v52, <32 x i32> undef, <32 x i32> %v46)
66  %v54 = tail call <64 x i32> @llvm.hexagon.V6.vmpabus.acc.128B(<64 x i32> %v42, <64 x i32> undef, i32 16843009)
67  %v55 = tail call <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32> %v53, <32 x i32> undef)
68  %v56 = tail call <64 x i32> @llvm.hexagon.V6.vmpabus.acc.128B(<64 x i32> %v54, <64 x i32> %v55, i32 16843009)
69  %v57 = tail call <32 x i32> @llvm.hexagon.V6.vaddbnq.128B(<128 x i1> %v50, <32 x i32> %v43, <32 x i32> %v0)
70  %v58 = tail call <32 x i32> @llvm.hexagon.V6.vaddbnq.128B(<128 x i1> %v51, <32 x i32> %v57, <32 x i32> %v0)
71  %v59 = tail call <32 x i32> @llvm.hexagon.V6.vaddbnq.128B(<128 x i1> undef, <32 x i32> %v58, <32 x i32> %v0)
72  %v60 = tail call <32 x i32> @llvm.hexagon.V6.vaddbnq.128B(<128 x i1> %v52, <32 x i32> %v59, <32 x i32> %v0)
73  %v61 = tail call <128 x i1> @llvm.hexagon.V6.vgtub.128B(<32 x i32> undef, <32 x i32> zeroinitializer)
74  %v62 = tail call <64 x i32> @llvm.hexagon.V6.vmpabus.acc.128B(<64 x i32> %v56, <64 x i32> undef, i32 16843009)
75  %v63 = tail call <64 x i32> @llvm.hexagon.V6.vmpabus.acc.128B(<64 x i32> %v62, <64 x i32> zeroinitializer, i32 16843009)
76  %v64 = tail call <32 x i32> @llvm.hexagon.V6.vaddbnq.128B(<128 x i1> undef, <32 x i32> %v60, <32 x i32> %v0)
77  %v65 = tail call <32 x i32> @llvm.hexagon.V6.vaddbnq.128B(<128 x i1> %v61, <32 x i32> %v64, <32 x i32> %v0)
78  %v66 = tail call <32 x i32> @llvm.hexagon.V6.vaddbnq.128B(<128 x i1> undef, <32 x i32> %v65, <32 x i32> %v0)
79  %v67 = tail call <32 x i32> @llvm.hexagon.V6.vaddbnq.128B(<128 x i1> undef, <32 x i32> %v66, <32 x i32> %v0)
80  %v68 = tail call <64 x i32> @llvm.hexagon.V6.vlutvwh.oracc.128B(<64 x i32> undef, <32 x i32> %v67, <32 x i32> %v1, i32 3)
81  %v69 = tail call <64 x i32> @llvm.hexagon.V6.vlutvwh.oracc.128B(<64 x i32> %v68, <32 x i32> %v67, <32 x i32> %v2, i32 4)
82  %v70 = tail call <64 x i32> @llvm.hexagon.V6.vlutvwh.oracc.128B(<64 x i32> %v69, <32 x i32> %v67, <32 x i32> %v2, i32 5)
83  %v71 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %v63)
84  %v72 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %v70)
85  %v73 = tail call <64 x i32> @llvm.hexagon.V6.vmpyuhv.128B(<32 x i32> %v71, <32 x i32> %v72)
86  %v74 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %v73)
87  %v75 = tail call <32 x i32> @llvm.hexagon.V6.vasrwh.128B(<32 x i32> %v74, <32 x i32> undef, i32 14)
88  %v76 = tail call <32 x i32> @llvm.hexagon.V6.vshuffeb.128B(<32 x i32> %v75, <32 x i32> undef)
89  store <32 x i32> %v76, <32 x i32>* %v6, align 128, !tbaa !0
90  %v77 = add nsw i32 %v5, 1
91  %v78 = icmp slt i32 %v77, %v3
92  br i1 %v78, label %b1, label %b2
93
94b2:                                               ; preds = %b1, %b0
95  ret void
96}
97
98; Function Attrs: nounwind readnone
99declare <32 x i32> @llvm.hexagon.V6.lvsplatw.128B(i32) #1
100
101; Function Attrs: nounwind readnone
102declare <32 x i32> @llvm.hexagon.V6.vshuffh.128B(<32 x i32>) #1
103
104; Function Attrs: nounwind readnone
105declare <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32>, <32 x i32>) #1
106
107; Function Attrs: nounwind readnone
108declare <32 x i32> @llvm.hexagon.V6.vabsdiffub.128B(<32 x i32>, <32 x i32>) #1
109
110; Function Attrs: nounwind readnone
111declare <128 x i1> @llvm.hexagon.V6.vgtub.128B(<32 x i32>, <32 x i32>) #1
112
113; Function Attrs: nounwind readnone
114declare <32 x i32> @llvm.hexagon.V6.vmux.128B(<128 x i1>, <32 x i32>, <32 x i32>) #1
115
116; Function Attrs: nounwind readnone
117declare <64 x i32> @llvm.hexagon.V6.vmpybus.acc.128B(<64 x i32>, <32 x i32>, i32) #1
118
119; Function Attrs: nounwind readnone
120declare <32 x i32> @llvm.hexagon.V6.vaddbnq.128B(<128 x i1>, <32 x i32>, <32 x i32>) #1
121
122; Function Attrs: nounwind readnone
123declare <32 x i32> @llvm.hexagon.V6.vlalignbi.128B(<32 x i32>, <32 x i32>, i32) #1
124
125; Function Attrs: nounwind readnone
126declare <32 x i32> @llvm.hexagon.V6.valignbi.128B(<32 x i32>, <32 x i32>, i32) #1
127
128; Function Attrs: nounwind readnone
129declare <64 x i32> @llvm.hexagon.V6.vmpabus.acc.128B(<64 x i32>, <64 x i32>, i32) #1
130
131; Function Attrs: nounwind readnone
132declare <64 x i32> @llvm.hexagon.V6.vlutvwh.oracc.128B(<64 x i32>, <32 x i32>, <32 x i32>, i32) #1
133
134; Function Attrs: nounwind readnone
135declare <64 x i32> @llvm.hexagon.V6.vmpyuhv.128B(<32 x i32>, <32 x i32>) #1
136
137; Function Attrs: nounwind readnone
138declare <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32>) #1
139
140; Function Attrs: nounwind readnone
141declare <32 x i32> @llvm.hexagon.V6.vasrwh.128B(<32 x i32>, <32 x i32>, i32) #1
142
143; Function Attrs: nounwind readnone
144declare <32 x i32> @llvm.hexagon.V6.vshuffeb.128B(<32 x i32>, <32 x i32>) #1
145
146attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" }
147attributes #1 = { nounwind readnone }
148
149!0 = !{!1, !1, i64 0}
150!1 = !{!"omnipotent char", !2, i64 0}
151!2 = !{!"Simple C/C++ TBAA"}
152