1; RUN: llc -march=hexagon < %s | FileCheck %s
2; CHECK: v{{[0-9]*}}.w = vadd
3
4target triple = "hexagon"
5
6@g0 = common global <16 x i32> zeroinitializer, align 64
7@g1 = common global <16 x i32> zeroinitializer, align 64
8@g2 = common global <16 x i32> zeroinitializer, align 64
9
10; Function Attrs: nounwind
11define void @f0() #0 {
12b0:
13  %v0 = load <16 x i32>, <16 x i32>* @g0, align 32, !tbaa !0
14  %v1 = load <16 x i32>, <16 x i32>* @g1, align 32, !tbaa !0
15  %v2 = tail call <16 x i32> @llvm.hexagon.V6.vaddw(<16 x i32> %v0, <16 x i32> %v1)
16  store <16 x i32> %v2, <16 x i32>* @g2, align 64, !tbaa !0
17  ret void
18}
19
20; Function Attrs: nounwind readnone
21declare <16 x i32> @llvm.hexagon.V6.vaddw(<16 x i32>, <16 x i32>) #1
22
23attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
24attributes #1 = { nounwind readnone }
25
26!0 = !{!1, !1, i64 0}
27!1 = !{!"omnipotent char", !2}
28!2 = !{!"Simple C/C++ TBAA"}
29