1; RUN: llc -march=hexagon < %s | FileCheck %s --check-prefix=CHECK-ASLW
2; RUN: llc -march=hexagon < %s | FileCheck %s --check-prefix=CHECK-ASRW
3; RUN: llc -march=hexagon < %s | FileCheck %s --check-prefix=CHECK-LSRW
4; RUN: llc -march=hexagon < %s | FileCheck %s --check-prefix=CHECK-ASLH
5; RUN: llc -march=hexagon < %s | FileCheck %s --check-prefix=CHECK-ASRH
6; RUN: llc -march=hexagon < %s | FileCheck %s --check-prefix=CHECK-LSRH
7;
8; Make sure that the instructions with immediate operands are generated.
9; CHECK-ASLW: vaslw({{.*}},#9)
10; CHECK-ASRW: vasrw({{.*}},#8)
11; CHECK-LSRW: vlsrw({{.*}},#7)
12; CHECK-ASLH: vaslh({{.*}},#6)
13; CHECK-ASRH: vasrh({{.*}},#5)
14; CHECK-LSRH: vlsrh({{.*}},#4)
15
16target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32"
17target triple = "hexagon"
18
19define i64 @foo(i64 %x) nounwind readnone {
20entry:
21  %0 = tail call i64 @llvm.hexagon.S2.asl.i.vw(i64 %x, i32 9)
22  %1 = tail call i64 @llvm.hexagon.S2.asr.i.vw(i64 %x, i32 8)
23  %2 = tail call i64 @llvm.hexagon.S2.lsr.i.vw(i64 %x, i32 7)
24  %3 = tail call i64 @llvm.hexagon.S2.asl.i.vh(i64 %x, i32 6)
25  %4 = tail call i64 @llvm.hexagon.S2.asr.i.vh(i64 %x, i32 5)
26  %5 = tail call i64 @llvm.hexagon.S2.lsr.i.vh(i64 %x, i32 4)
27  %add = add i64 %1, %0
28  %add1 = add i64 %add, %2
29  %add2 = add i64 %add1, %3
30  %add3 = add i64 %add2, %4
31  %add4 = add i64 %add3, %5
32  ret i64 %add4
33}
34
35declare i64 @llvm.hexagon.S2.asl.i.vw(i64, i32) nounwind readnone
36declare i64 @llvm.hexagon.S2.asr.i.vw(i64, i32) nounwind readnone
37declare i64 @llvm.hexagon.S2.lsr.i.vw(i64, i32) nounwind readnone
38declare i64 @llvm.hexagon.S2.asl.i.vh(i64, i32) nounwind readnone
39declare i64 @llvm.hexagon.S2.asr.i.vh(i64, i32) nounwind readnone
40declare i64 @llvm.hexagon.S2.lsr.i.vh(i64, i32) nounwind readnone
41
42