1; RUN: llc -march=hexagon -hexagon-instsimplify=0 < %s | FileCheck %s
2
3; Check that this compiles successfully.
4; CHECK: vcmph.eq
5
6target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
7target triple = "hexagon"
8
9define i32 @fred(<8 x i16>* %a0) #0 {
10b0:
11  switch i32 undef, label %b14 [
12    i32 5, label %b2
13    i32 3, label %b1
14  ]
15
16b1:                                               ; preds = %b0
17  br label %b14
18
19b2:                                               ; preds = %b0
20  %v2 = load <8 x i16>, <8 x i16>* %a0, align 64
21  %v3 = icmp eq <8 x i16> %v2, zeroinitializer
22  %v4 = zext <8 x i1> %v3 to <8 x i16>
23  %v5 = add <8 x i16> zeroinitializer, %v4
24  %v6 = add <8 x i16> %v5, zeroinitializer
25  %v7 = add <8 x i16> %v6, zeroinitializer
26  %v8 = extractelement <8 x i16> %v7, i32 0
27  %v9 = add i16 %v8, 0
28  %v10 = add i16 %v9, 0
29  %v11 = add i16 %v10, 0
30  %v12 = icmp eq i16 %v11, 11
31  br i1 %v12, label %b14, label %b13
32
33b13:                                              ; preds = %b2
34  ret i32 1
35
36b14:                                              ; preds = %b2, %b1, %b0
37  ret i32 0
38}
39
40attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx-length64b,+hvxv60" }
41