1; RUN: llc -march=hexagon < %s | FileCheck %s
2
3; Check that the store to Q6VecPredResult does not get expanded into multiple
4; stores. There should be no memd's. This relies on the alignment specified
5; in the data layout string, so don't provide one here to make sure that the
6; default one from HexagonTargetMachine is correct.
7
8; CHECK-NOT: memd
9
10
11@Q6VecPredResult = common global <16 x i32> zeroinitializer, align 64
12
13define i32 @foo() #0 {
14entry:
15  %v0 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 1)
16  %v1 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %v0, i32 -2147483648)
17  %v2 = tail call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %v1, i32 -1)
18  store <16 x i32> %v2, <16 x i32>* @Q6VecPredResult, align 64, !tbaa !1
19  tail call void @print_vecpred(i32 64, i8* bitcast (<16 x i32>* @Q6VecPredResult to i8*)) #3
20  ret i32 0
21}
22
23declare <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32>, i32) #1
24declare <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1>, i32) #1
25declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #1
26
27declare void @print_vecpred(i32, i8*) #2
28
29attributes #0 = { nounwind "target-cpu"="hexagonv66" "target-features"="+hvxv66,+hvx-length64b" }
30attributes #1 = { nounwind readnone }
31attributes #2 = { nounwind }
32
33!1 = !{!2, !2, i64 0}
34!2 = !{!"omnipotent char", !3, i64 0}
35!3 = !{!"Simple C/C++ TBAA"}
36