1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=mips-- -mattr=-fp64 | FileCheck %s -check-prefix=CHECK-FP32
3; RUN: llc < %s -mtriple=mips-- -mcpu=mips32r2 -mattr=+fp64 | FileCheck %s -check-prefix=CHECK-FP64
4
5; This test case is a simplified version of an llvm-stress generated test with
6; seed=3718491962.
7; It originally failed on MIPS32 with FP64 with the following error:
8;     LLVM ERROR: ran out of registers during register allocation
9; This was caused by impossible register class restrictions caused by the use
10; of BuildPairF64 instead of BuildPairF64_64.
11
12; FIXME: A redundant mthc1 is currently emitted.
13define void @autogen_SD3718491962(double %a0) {
14; CHECK-FP32-LABEL: autogen_SD3718491962:
15; CHECK-FP32:       # %bb.0: # %BB
16; CHECK-FP32-NEXT:    lui $1, %hi($CPI0_0)
17; CHECK-FP32-NEXT:    ldc1 $f0, %lo($CPI0_0)($1)
18; CHECK-FP32-NEXT:    mtc1 $zero, $f2
19; CHECK-FP32-NEXT:    mtc1 $zero, $f3
20; CHECK-FP32-NEXT:  $BB0_1: # %CF88
21; CHECK-FP32-NEXT:    # =>This Inner Loop Header: Depth=1
22; CHECK-FP32-NEXT:    c.ueq.d $f12, $f0
23; CHECK-FP32-NEXT:    addiu $1, $zero, 1
24; CHECK-FP32-NEXT:    movf $1, $zero, $fcc0
25; CHECK-FP32-NEXT:    c.olt.d $f12, $f2
26; CHECK-FP32-NEXT:    addiu $2, $zero, 1
27; CHECK-FP32-NEXT:    movt $2, $zero, $fcc0
28; CHECK-FP32-NEXT:    and $1, $2, $1
29; CHECK-FP32-NEXT:    bnez $1, $BB0_1
30; CHECK-FP32-NEXT:    nop
31; CHECK-FP32-NEXT:  # %bb.2: # %CF85
32; CHECK-FP32-NEXT:    jr $ra
33; CHECK-FP32-NEXT:    nop
34;
35; CHECK-FP64-LABEL: autogen_SD3718491962:
36; CHECK-FP64:       # %bb.0: # %BB
37; CHECK-FP64-NEXT:    lui $1, %hi($CPI0_0)
38; CHECK-FP64-NEXT:    ldc1 $f0, %lo($CPI0_0)($1)
39; CHECK-FP64-NEXT:    mtc1 $zero, $f1
40; CHECK-FP64-NEXT:    mthc1 $zero, $f1
41; CHECK-FP64-NEXT:  $BB0_1: # %CF88
42; CHECK-FP64-NEXT:    # =>This Inner Loop Header: Depth=1
43; CHECK-FP64-NEXT:    c.ueq.d $f12, $f0
44; CHECK-FP64-NEXT:    addiu $1, $zero, 1
45; CHECK-FP64-NEXT:    movf $1, $zero, $fcc0
46; CHECK-FP64-NEXT:    c.olt.d $f12, $f1
47; CHECK-FP64-NEXT:    addiu $2, $zero, 1
48; CHECK-FP64-NEXT:    movt $2, $zero, $fcc0
49; CHECK-FP64-NEXT:    and $1, $2, $1
50; CHECK-FP64-NEXT:    bnez $1, $BB0_1
51; CHECK-FP64-NEXT:    nop
52; CHECK-FP64-NEXT:  # %bb.2: # %CF85
53; CHECK-FP64-NEXT:    jr $ra
54; CHECK-FP64-NEXT:    nop
55BB:
56  %Cmp = fcmp ule double 0.000000e+00, %a0
57  %Cmp11 = fcmp ueq double 0xFDBD965CF1BB7FDA, %a0
58  br label %CF88
59
60CF88:                                             ; preds = %CF86
61  %Sl18 = select i1 %Cmp, i1 %Cmp11, i1 %Cmp
62  br i1 %Sl18, label %CF88, label %CF85
63
64CF85:                                             ; preds = %CF88
65  ret void
66}
67