1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
3# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
4--- |
5
6  define void @f32toi32() {entry: ret void}
7  define void @f64toi32() {entry: ret void}
8
9...
10---
11name:            f32toi32
12alignment:       4
13legalized:       true
14tracksRegLiveness: true
15body:             |
16  bb.1.entry:
17    liveins: $f12
18
19    ; FP32-LABEL: name: f32toi32
20    ; FP32: liveins: $f12
21    ; FP32: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12
22    ; FP32: [[FPTOSI:%[0-9]+]]:gprb(s32) = G_FPTOSI [[COPY]](s32)
23    ; FP32: $v0 = COPY [[FPTOSI]](s32)
24    ; FP32: RetRA implicit $v0
25    ; FP64-LABEL: name: f32toi32
26    ; FP64: liveins: $f12
27    ; FP64: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12
28    ; FP64: [[FPTOSI:%[0-9]+]]:gprb(s32) = G_FPTOSI [[COPY]](s32)
29    ; FP64: $v0 = COPY [[FPTOSI]](s32)
30    ; FP64: RetRA implicit $v0
31    %0:_(s32) = COPY $f12
32    %1:_(s32) = G_FPTOSI %0(s32)
33    $v0 = COPY %1(s32)
34    RetRA implicit $v0
35
36...
37---
38name:            f64toi32
39alignment:       4
40legalized:       true
41tracksRegLiveness: true
42body:             |
43  bb.1.entry:
44    liveins: $d6
45
46    ; FP32-LABEL: name: f64toi32
47    ; FP32: liveins: $d6
48    ; FP32: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d6
49    ; FP32: [[FPTOSI:%[0-9]+]]:gprb(s32) = G_FPTOSI [[COPY]](s64)
50    ; FP32: $v0 = COPY [[FPTOSI]](s32)
51    ; FP32: RetRA implicit $v0
52    ; FP64-LABEL: name: f64toi32
53    ; FP64: liveins: $d6
54    ; FP64: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d6
55    ; FP64: [[FPTOSI:%[0-9]+]]:gprb(s32) = G_FPTOSI [[COPY]](s64)
56    ; FP64: $v0 = COPY [[FPTOSI]](s32)
57    ; FP64: RetRA implicit $v0
58    %0:_(s64) = COPY $d6
59    %1:_(s32) = G_FPTOSI %0(s64)
60    $v0 = COPY %1(s32)
61    RetRA implicit $v0
62
63...
64