1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600 3--- | 4 5 define void @sqrt_v4f32(<4 x float>* %a, <4 x float>* %c) { entry: ret void } 6 define void @sqrt_v2f64(<2 x double>* %a, <2 x double>* %c) { entry: ret void } 7 8... 9--- 10name: sqrt_v4f32 11alignment: 4 12legalized: true 13tracksRegLiveness: true 14body: | 15 bb.1.entry: 16 liveins: $a0, $a1 17 18 ; P5600-LABEL: name: sqrt_v4f32 19 ; P5600: liveins: $a0, $a1 20 ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0 21 ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1 22 ; P5600: [[LOAD:%[0-9]+]]:fprb(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a) 23 ; P5600: [[FSQRT:%[0-9]+]]:fprb(<4 x s32>) = G_FSQRT [[LOAD]] 24 ; P5600: G_STORE [[FSQRT]](<4 x s32>), [[COPY1]](p0) :: (store 16 into %ir.c) 25 ; P5600: RetRA 26 %0:_(p0) = COPY $a0 27 %1:_(p0) = COPY $a1 28 %2:_(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.a) 29 %3:_(<4 x s32>) = G_FSQRT %2 30 G_STORE %3(<4 x s32>), %1(p0) :: (store 16 into %ir.c) 31 RetRA 32 33... 34--- 35name: sqrt_v2f64 36alignment: 4 37legalized: true 38tracksRegLiveness: true 39body: | 40 bb.1.entry: 41 liveins: $a0, $a1 42 43 ; P5600-LABEL: name: sqrt_v2f64 44 ; P5600: liveins: $a0, $a1 45 ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0 46 ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1 47 ; P5600: [[LOAD:%[0-9]+]]:fprb(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a) 48 ; P5600: [[FSQRT:%[0-9]+]]:fprb(<2 x s64>) = G_FSQRT [[LOAD]] 49 ; P5600: G_STORE [[FSQRT]](<2 x s64>), [[COPY1]](p0) :: (store 16 into %ir.c) 50 ; P5600: RetRA 51 %0:_(p0) = COPY $a0 52 %1:_(p0) = COPY $a1 53 %2:_(<2 x s64>) = G_LOAD %0(p0) :: (load 16 from %ir.a) 54 %3:_(<2 x s64>) = G_FSQRT %2 55 G_STORE %3(<2 x s64>), %1(p0) :: (store 16 into %ir.c) 56 RetRA 57 58... 59