1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
3--- |
4
5  define i32 @phi_i32(i1 %cnd, i32 %a, i32 %b) {
6  entry:
7    br i1 %cnd, label %cond.true, label %cond.false
8
9  cond.true:                                        ; preds = %entry
10    br label %cond.end
11
12  cond.false:                                       ; preds = %entry
13    br label %cond.end
14
15  cond.end:                                         ; preds = %cond.false, %cond.true
16    %cond = phi i32 [ %a, %cond.true ], [ %b, %cond.false ]
17    ret i32 %cond
18  }
19
20  define i64 @phi_i64(i1 %cnd, i64 %a, i64 %b) {
21  entry:
22    br i1 %cnd, label %cond.true, label %cond.false
23
24  cond.true:                                        ; preds = %entry
25    br label %cond.end
26
27  cond.false:                                       ; preds = %entry
28    br label %cond.end
29
30  cond.end:                                         ; preds = %cond.false, %cond.true
31    %cond = phi i64 [ %a, %cond.true ], [ %b, %cond.false ]
32    ret i64 %cond
33  }
34
35  define void @phi_ambiguous_i64_in_fpr(i1 %cnd, i64* %i64_ptr_a, i64* %i64_ptr_b, i64* %i64_ptr_c) {
36  entry:
37    %0 = load i64, i64* %i64_ptr_a, align 8
38    %1 = load i64, i64* %i64_ptr_b, align 8
39    br i1 %cnd, label %cond.true, label %cond.false
40
41  cond.true:                                        ; preds = %entry
42    br label %cond.end
43
44  cond.false:                                       ; preds = %entry
45    br label %cond.end
46
47  cond.end:                                         ; preds = %cond.false, %cond.true
48    %cond = phi i64 [ %0, %cond.true ], [ %1, %cond.false ]
49    store i64 %cond, i64* %i64_ptr_c, align 8
50    ret void
51  }
52
53  define float @phi_float(i1 %cnd, float %a, float %b) {
54  entry:
55    br i1 %cnd, label %cond.true, label %cond.false
56
57  cond.true:                                        ; preds = %entry
58    br label %cond.end
59
60  cond.false:                                       ; preds = %entry
61    br label %cond.end
62
63  cond.end:                                         ; preds = %cond.false, %cond.true
64    %cond = phi float [ %a, %cond.true ], [ %b, %cond.false ]
65    ret float %cond
66  }
67
68  define void @phi_ambiguous_float_in_gpr(i1 %cnd, float* %f32_ptr_a, float* %f32_ptr_b, float* %f32_ptr_c) {
69  entry:
70    %0 = load float, float* %f32_ptr_a, align 4
71    %1 = load float, float* %f32_ptr_b, align 4
72    br i1 %cnd, label %cond.true, label %cond.false
73
74  cond.true:                                        ; preds = %entry
75    br label %cond.end
76
77  cond.false:                                       ; preds = %entry
78    br label %cond.end
79
80  cond.end:                                         ; preds = %cond.false, %cond.true
81    %cond = phi float [ %0, %cond.true ], [ %1, %cond.false ]
82    store float %cond, float* %f32_ptr_c, align 4
83    ret void
84  }
85
86  define double @phi_double(double %a, double %b, i1 %cnd) {
87  entry:
88    br i1 %cnd, label %cond.true, label %cond.false
89
90  cond.true:                                        ; preds = %entry
91    br label %cond.end
92
93  cond.false:                                       ; preds = %entry
94    br label %cond.end
95
96  cond.end:                                         ; preds = %cond.false, %cond.true
97    %cond = phi double [ %a, %cond.true ], [ %b, %cond.false ]
98    ret double %cond
99  }
100
101...
102---
103name:            phi_i32
104alignment:       4
105legalized:       true
106tracksRegLiveness: true
107body:             |
108  ; MIPS32-LABEL: name: phi_i32
109  ; MIPS32: bb.0.entry:
110  ; MIPS32:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
111  ; MIPS32:   liveins: $a0, $a1, $a2
112  ; MIPS32:   [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
113  ; MIPS32:   [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
114  ; MIPS32:   [[COPY2:%[0-9]+]]:gprb(s32) = COPY $a2
115  ; MIPS32:   [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
116  ; MIPS32:   [[COPY3:%[0-9]+]]:gprb(s32) = COPY [[COPY]](s32)
117  ; MIPS32:   [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY3]], [[C]]
118  ; MIPS32:   G_BRCOND [[AND]](s32), %bb.1
119  ; MIPS32:   G_BR %bb.2
120  ; MIPS32: bb.1.cond.true:
121  ; MIPS32:   successors: %bb.3(0x80000000)
122  ; MIPS32:   G_BR %bb.3
123  ; MIPS32: bb.2.cond.false:
124  ; MIPS32:   successors: %bb.3(0x80000000)
125  ; MIPS32: bb.3.cond.end:
126  ; MIPS32:   [[PHI:%[0-9]+]]:gprb(s32) = G_PHI [[COPY1]](s32), %bb.1, [[COPY2]](s32), %bb.2
127  ; MIPS32:   $v0 = COPY [[PHI]](s32)
128  ; MIPS32:   RetRA implicit $v0
129  bb.1.entry:
130    liveins: $a0, $a1, $a2
131
132    %3:_(s32) = COPY $a0
133    %1:_(s32) = COPY $a1
134    %2:_(s32) = COPY $a2
135    %6:_(s32) = G_CONSTANT i32 1
136    %7:_(s32) = COPY %3(s32)
137    %5:_(s32) = G_AND %7, %6
138    G_BRCOND %5(s32), %bb.2
139    G_BR %bb.3
140
141  bb.2.cond.true:
142    G_BR %bb.4
143
144  bb.3.cond.false:
145
146  bb.4.cond.end:
147    %4:_(s32) = G_PHI %1(s32), %bb.2, %2(s32), %bb.3
148    $v0 = COPY %4(s32)
149    RetRA implicit $v0
150
151...
152---
153name:            phi_i64
154alignment:       4
155legalized:       true
156tracksRegLiveness: true
157fixedStack:
158  - { id: 0, offset: 20, size: 4, alignment: 4, isImmutable: true }
159  - { id: 1, offset: 16, size: 4, alignment: 8, isImmutable: true }
160body:             |
161  ; MIPS32-LABEL: name: phi_i64
162  ; MIPS32: bb.0.entry:
163  ; MIPS32:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
164  ; MIPS32:   liveins: $a0, $a2, $a3
165  ; MIPS32:   [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
166  ; MIPS32:   [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a2
167  ; MIPS32:   [[COPY2:%[0-9]+]]:gprb(s32) = COPY $a3
168  ; MIPS32:   [[FRAME_INDEX:%[0-9]+]]:gprb(p0) = G_FRAME_INDEX %fixed-stack.0
169  ; MIPS32:   [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load 4 from %fixed-stack.0, align 8)
170  ; MIPS32:   [[FRAME_INDEX1:%[0-9]+]]:gprb(p0) = G_FRAME_INDEX %fixed-stack.1
171  ; MIPS32:   [[LOAD1:%[0-9]+]]:gprb(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (load 4 from %fixed-stack.1)
172  ; MIPS32:   [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
173  ; MIPS32:   [[COPY3:%[0-9]+]]:gprb(s32) = COPY [[COPY]](s32)
174  ; MIPS32:   [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY3]], [[C]]
175  ; MIPS32:   G_BRCOND [[AND]](s32), %bb.1
176  ; MIPS32:   G_BR %bb.2
177  ; MIPS32: bb.1.cond.true:
178  ; MIPS32:   successors: %bb.3(0x80000000)
179  ; MIPS32:   G_BR %bb.3
180  ; MIPS32: bb.2.cond.false:
181  ; MIPS32:   successors: %bb.3(0x80000000)
182  ; MIPS32: bb.3.cond.end:
183  ; MIPS32:   [[PHI:%[0-9]+]]:gprb(s32) = G_PHI [[COPY1]](s32), %bb.1, [[LOAD]](s32), %bb.2
184  ; MIPS32:   [[PHI1:%[0-9]+]]:gprb(s32) = G_PHI [[COPY2]](s32), %bb.1, [[LOAD1]](s32), %bb.2
185  ; MIPS32:   $v0 = COPY [[PHI]](s32)
186  ; MIPS32:   $v1 = COPY [[PHI1]](s32)
187  ; MIPS32:   RetRA implicit $v0, implicit $v1
188  bb.1.entry:
189    liveins: $a0, $a2, $a3
190
191    %3:_(s32) = COPY $a0
192    %4:_(s32) = COPY $a2
193    %5:_(s32) = COPY $a3
194    %1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
195    %8:_(p0) = G_FRAME_INDEX %fixed-stack.1
196    %6:_(s32) = G_LOAD %8(p0) :: (load 4 from %fixed-stack.1, align 8)
197    %9:_(p0) = G_FRAME_INDEX %fixed-stack.0
198    %7:_(s32) = G_LOAD %9(p0) :: (load 4 from %fixed-stack.0)
199    %2:_(s64) = G_MERGE_VALUES %6(s32), %7(s32)
200    %14:_(s32) = G_CONSTANT i32 1
201    %15:_(s32) = COPY %3(s32)
202    %13:_(s32) = G_AND %15, %14
203    G_BRCOND %13(s32), %bb.2
204    G_BR %bb.3
205
206  bb.2.cond.true:
207    G_BR %bb.4
208
209  bb.3.cond.false:
210
211  bb.4.cond.end:
212    %10:_(s64) = G_PHI %1(s64), %bb.2, %2(s64), %bb.3
213    %11:_(s32), %12:_(s32) = G_UNMERGE_VALUES %10(s64)
214    $v0 = COPY %11(s32)
215    $v1 = COPY %12(s32)
216    RetRA implicit $v0, implicit $v1
217
218...
219---
220name:            phi_ambiguous_i64_in_fpr
221alignment:       4
222legalized:       true
223tracksRegLiveness: true
224body:             |
225  ; MIPS32-LABEL: name: phi_ambiguous_i64_in_fpr
226  ; MIPS32: bb.0.entry:
227  ; MIPS32:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
228  ; MIPS32:   liveins: $a0, $a1, $a2, $a3
229  ; MIPS32:   [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
230  ; MIPS32:   [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
231  ; MIPS32:   [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
232  ; MIPS32:   [[COPY3:%[0-9]+]]:gprb(p0) = COPY $a3
233  ; MIPS32:   [[LOAD:%[0-9]+]]:fprb(s64) = G_LOAD [[COPY1]](p0) :: (load 8 from %ir.i64_ptr_a)
234  ; MIPS32:   [[LOAD1:%[0-9]+]]:fprb(s64) = G_LOAD [[COPY2]](p0) :: (load 8 from %ir.i64_ptr_b)
235  ; MIPS32:   [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
236  ; MIPS32:   [[COPY4:%[0-9]+]]:gprb(s32) = COPY [[COPY]](s32)
237  ; MIPS32:   [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY4]], [[C]]
238  ; MIPS32:   G_BRCOND [[AND]](s32), %bb.1
239  ; MIPS32:   G_BR %bb.2
240  ; MIPS32: bb.1.cond.true:
241  ; MIPS32:   successors: %bb.3(0x80000000)
242  ; MIPS32:   G_BR %bb.3
243  ; MIPS32: bb.2.cond.false:
244  ; MIPS32:   successors: %bb.3(0x80000000)
245  ; MIPS32: bb.3.cond.end:
246  ; MIPS32:   [[PHI:%[0-9]+]]:fprb(s64) = G_PHI [[LOAD]](s64), %bb.1, [[LOAD1]](s64), %bb.2
247  ; MIPS32:   G_STORE [[PHI]](s64), [[COPY3]](p0) :: (store 8 into %ir.i64_ptr_c)
248  ; MIPS32:   RetRA
249  bb.1.entry:
250    liveins: $a0, $a1, $a2, $a3
251
252    %4:_(s32) = COPY $a0
253    %1:_(p0) = COPY $a1
254    %2:_(p0) = COPY $a2
255    %3:_(p0) = COPY $a3
256    %5:_(s64) = G_LOAD %1(p0) :: (load 8 from %ir.i64_ptr_a)
257    %6:_(s64) = G_LOAD %2(p0) :: (load 8 from %ir.i64_ptr_b)
258    %9:_(s32) = G_CONSTANT i32 1
259    %10:_(s32) = COPY %4(s32)
260    %8:_(s32) = G_AND %10, %9
261    G_BRCOND %8(s32), %bb.2
262    G_BR %bb.3
263
264  bb.2.cond.true:
265    G_BR %bb.4
266
267  bb.3.cond.false:
268
269  bb.4.cond.end:
270    %7:_(s64) = G_PHI %5(s64), %bb.2, %6(s64), %bb.3
271    G_STORE %7(s64), %3(p0) :: (store 8 into %ir.i64_ptr_c)
272    RetRA
273
274...
275---
276name:            phi_float
277alignment:       4
278legalized:       true
279tracksRegLiveness: true
280body:             |
281  ; MIPS32-LABEL: name: phi_float
282  ; MIPS32: bb.0.entry:
283  ; MIPS32:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
284  ; MIPS32:   liveins: $a0, $a1, $a2
285  ; MIPS32:   [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
286  ; MIPS32:   [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
287  ; MIPS32:   [[COPY2:%[0-9]+]]:gprb(s32) = COPY $a2
288  ; MIPS32:   [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
289  ; MIPS32:   [[COPY3:%[0-9]+]]:gprb(s32) = COPY [[COPY]](s32)
290  ; MIPS32:   [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY3]], [[C]]
291  ; MIPS32:   G_BRCOND [[AND]](s32), %bb.1
292  ; MIPS32:   G_BR %bb.2
293  ; MIPS32: bb.1.cond.true:
294  ; MIPS32:   successors: %bb.3(0x80000000)
295  ; MIPS32:   G_BR %bb.3
296  ; MIPS32: bb.2.cond.false:
297  ; MIPS32:   successors: %bb.3(0x80000000)
298  ; MIPS32: bb.3.cond.end:
299  ; MIPS32:   [[PHI:%[0-9]+]]:gprb(s32) = G_PHI [[COPY1]](s32), %bb.1, [[COPY2]](s32), %bb.2
300  ; MIPS32:   $f0 = COPY [[PHI]](s32)
301  ; MIPS32:   RetRA implicit $f0
302  bb.1.entry:
303    liveins: $a0, $a1, $a2
304
305    %3:_(s32) = COPY $a0
306    %1:_(s32) = COPY $a1
307    %2:_(s32) = COPY $a2
308    %6:_(s32) = G_CONSTANT i32 1
309    %7:_(s32) = COPY %3(s32)
310    %5:_(s32) = G_AND %7, %6
311    G_BRCOND %5(s32), %bb.2
312    G_BR %bb.3
313
314  bb.2.cond.true:
315    G_BR %bb.4
316
317  bb.3.cond.false:
318
319  bb.4.cond.end:
320    %4:_(s32) = G_PHI %1(s32), %bb.2, %2(s32), %bb.3
321    $f0 = COPY %4(s32)
322    RetRA implicit $f0
323
324...
325---
326name:            phi_ambiguous_float_in_gpr
327alignment:       4
328legalized:       true
329tracksRegLiveness: true
330body:             |
331  ; MIPS32-LABEL: name: phi_ambiguous_float_in_gpr
332  ; MIPS32: bb.0.entry:
333  ; MIPS32:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
334  ; MIPS32:   liveins: $a0, $a1, $a2, $a3
335  ; MIPS32:   [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
336  ; MIPS32:   [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
337  ; MIPS32:   [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
338  ; MIPS32:   [[COPY3:%[0-9]+]]:gprb(p0) = COPY $a3
339  ; MIPS32:   [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY1]](p0) :: (load 4 from %ir.f32_ptr_a)
340  ; MIPS32:   [[LOAD1:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY2]](p0) :: (load 4 from %ir.f32_ptr_b)
341  ; MIPS32:   [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
342  ; MIPS32:   [[COPY4:%[0-9]+]]:gprb(s32) = COPY [[COPY]](s32)
343  ; MIPS32:   [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY4]], [[C]]
344  ; MIPS32:   G_BRCOND [[AND]](s32), %bb.1
345  ; MIPS32:   G_BR %bb.2
346  ; MIPS32: bb.1.cond.true:
347  ; MIPS32:   successors: %bb.3(0x80000000)
348  ; MIPS32:   G_BR %bb.3
349  ; MIPS32: bb.2.cond.false:
350  ; MIPS32:   successors: %bb.3(0x80000000)
351  ; MIPS32: bb.3.cond.end:
352  ; MIPS32:   [[PHI:%[0-9]+]]:gprb(s32) = G_PHI [[LOAD]](s32), %bb.1, [[LOAD1]](s32), %bb.2
353  ; MIPS32:   G_STORE [[PHI]](s32), [[COPY3]](p0) :: (store 4 into %ir.f32_ptr_c)
354  ; MIPS32:   RetRA
355  bb.1.entry:
356    liveins: $a0, $a1, $a2, $a3
357
358    %4:_(s32) = COPY $a0
359    %1:_(p0) = COPY $a1
360    %2:_(p0) = COPY $a2
361    %3:_(p0) = COPY $a3
362    %5:_(s32) = G_LOAD %1(p0) :: (load 4 from %ir.f32_ptr_a)
363    %6:_(s32) = G_LOAD %2(p0) :: (load 4 from %ir.f32_ptr_b)
364    %9:_(s32) = G_CONSTANT i32 1
365    %10:_(s32) = COPY %4(s32)
366    %8:_(s32) = G_AND %10, %9
367    G_BRCOND %8(s32), %bb.2
368    G_BR %bb.3
369
370  bb.2.cond.true:
371    G_BR %bb.4
372
373  bb.3.cond.false:
374
375  bb.4.cond.end:
376    %7:_(s32) = G_PHI %5(s32), %bb.2, %6(s32), %bb.3
377    G_STORE %7(s32), %3(p0) :: (store 4 into %ir.f32_ptr_c)
378    RetRA
379
380...
381---
382name:            phi_double
383alignment:       4
384legalized:       true
385tracksRegLiveness: true
386fixedStack:
387  - { id: 0, offset: 16, size: 4, alignment: 8, isImmutable: true }
388body:             |
389  ; MIPS32-LABEL: name: phi_double
390  ; MIPS32: bb.0.entry:
391  ; MIPS32:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
392  ; MIPS32:   liveins: $d6, $d7
393  ; MIPS32:   [[COPY:%[0-9]+]]:fprb(s64) = COPY $d6
394  ; MIPS32:   [[COPY1:%[0-9]+]]:fprb(s64) = COPY $d7
395  ; MIPS32:   [[FRAME_INDEX:%[0-9]+]]:gprb(p0) = G_FRAME_INDEX %fixed-stack.0
396  ; MIPS32:   [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load 4 from %fixed-stack.0, align 8)
397  ; MIPS32:   [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
398  ; MIPS32:   [[COPY2:%[0-9]+]]:gprb(s32) = COPY [[LOAD]](s32)
399  ; MIPS32:   [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY2]], [[C]]
400  ; MIPS32:   G_BRCOND [[AND]](s32), %bb.1
401  ; MIPS32:   G_BR %bb.2
402  ; MIPS32: bb.1.cond.true:
403  ; MIPS32:   successors: %bb.3(0x80000000)
404  ; MIPS32:   G_BR %bb.3
405  ; MIPS32: bb.2.cond.false:
406  ; MIPS32:   successors: %bb.3(0x80000000)
407  ; MIPS32: bb.3.cond.end:
408  ; MIPS32:   [[PHI:%[0-9]+]]:fprb(s64) = G_PHI [[COPY]](s64), %bb.1, [[COPY1]](s64), %bb.2
409  ; MIPS32:   $d0 = COPY [[PHI]](s64)
410  ; MIPS32:   RetRA implicit $d0
411  bb.1.entry:
412    liveins: $d6, $d7
413
414    %0:_(s64) = COPY $d6
415    %1:_(s64) = COPY $d7
416    %4:_(p0) = G_FRAME_INDEX %fixed-stack.0
417    %3:_(s32) = G_LOAD %4(p0) :: (load 4 from %fixed-stack.0, align 8)
418    %7:_(s32) = G_CONSTANT i32 1
419    %8:_(s32) = COPY %3(s32)
420    %6:_(s32) = G_AND %8, %7
421    G_BRCOND %6(s32), %bb.2
422    G_BR %bb.3
423
424  bb.2.cond.true:
425    G_BR %bb.4
426
427  bb.3.cond.false:
428
429  bb.4.cond.end:
430    %5:_(s64) = G_PHI %0(s64), %bb.2, %1(s64), %bb.3
431    $d0 = COPY %5(s64)
432    RetRA implicit $d0
433
434...
435