1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
3--- |
4
5  define void @load1_s8_to_zextLoad1_s32(i8* %px) {entry: ret void}
6  define void @load2_s16_to_zextLoad2_s32(i16* %px) {entry: ret void}
7  define void @load4_s32_to_zextLoad4_s64(i8* %px) {entry: ret void}
8  define void @load1_s8_to_sextLoad1_s32(i8* %px) {entry: ret void}
9  define void @load2_s16_to_sextLoad2_s32(i16* %px) {entry: ret void}
10  define void @load4_s32_to_sextLoad4_s64(i8* %px) {entry: ret void}
11
12...
13---
14name:            load1_s8_to_zextLoad1_s32
15alignment:       4
16legalized:       true
17tracksRegLiveness: true
18body:             |
19  bb.1.entry:
20    liveins: $a0
21
22    ; MIPS32-LABEL: name: load1_s8_to_zextLoad1_s32
23    ; MIPS32: liveins: $a0
24    ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
25    ; MIPS32: [[ZEXTLOAD:%[0-9]+]]:gprb(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 1 from %ir.px)
26    ; MIPS32: $v0 = COPY [[ZEXTLOAD]](s32)
27    ; MIPS32: RetRA implicit $v0
28    %0:_(p0) = COPY $a0
29    %2:_(s32) = G_ZEXTLOAD %0(p0) :: (load 1 from %ir.px)
30    $v0 = COPY %2(s32)
31    RetRA implicit $v0
32
33...
34---
35name:            load2_s16_to_zextLoad2_s32
36alignment:       4
37legalized:       true
38tracksRegLiveness: true
39body:             |
40  bb.1.entry:
41    liveins: $a0
42
43    ; MIPS32-LABEL: name: load2_s16_to_zextLoad2_s32
44    ; MIPS32: liveins: $a0
45    ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
46    ; MIPS32: [[ZEXTLOAD:%[0-9]+]]:gprb(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 2 from %ir.px)
47    ; MIPS32: $v0 = COPY [[ZEXTLOAD]](s32)
48    ; MIPS32: RetRA implicit $v0
49    %0:_(p0) = COPY $a0
50    %2:_(s32) = G_ZEXTLOAD %0(p0) :: (load 2 from %ir.px)
51    $v0 = COPY %2(s32)
52    RetRA implicit $v0
53
54...
55---
56name:            load4_s32_to_zextLoad4_s64
57alignment:       4
58legalized:       true
59tracksRegLiveness: true
60body:             |
61  bb.1.entry:
62    liveins: $a0
63
64    ; MIPS32-LABEL: name: load4_s32_to_zextLoad4_s64
65    ; MIPS32: liveins: $a0
66    ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
67    ; MIPS32: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.px)
68    ; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0
69    ; MIPS32: $v0 = COPY [[LOAD]](s32)
70    ; MIPS32: $v1 = COPY [[C]](s32)
71    ; MIPS32: RetRA implicit $v0, implicit $v1
72    %0:_(p0) = COPY $a0
73    %5:_(s32) = G_LOAD %0(p0) :: (load 4 from %ir.px)
74    %6:_(s32) = G_CONSTANT i32 0
75    %2:_(s64) = G_MERGE_VALUES %5(s32), %6(s32)
76    %3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
77    $v0 = COPY %3(s32)
78    $v1 = COPY %4(s32)
79    RetRA implicit $v0, implicit $v1
80
81...
82---
83name:            load1_s8_to_sextLoad1_s32
84alignment:       4
85legalized:       true
86tracksRegLiveness: true
87body:             |
88  bb.1.entry:
89    liveins: $a0
90
91    ; MIPS32-LABEL: name: load1_s8_to_sextLoad1_s32
92    ; MIPS32: liveins: $a0
93    ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
94    ; MIPS32: [[SEXTLOAD:%[0-9]+]]:gprb(s32) = G_SEXTLOAD [[COPY]](p0) :: (load 1 from %ir.px)
95    ; MIPS32: $v0 = COPY [[SEXTLOAD]](s32)
96    ; MIPS32: RetRA implicit $v0
97    %0:_(p0) = COPY $a0
98    %2:_(s32) = G_SEXTLOAD %0(p0) :: (load 1 from %ir.px)
99    $v0 = COPY %2(s32)
100    RetRA implicit $v0
101
102...
103---
104name:            load2_s16_to_sextLoad2_s32
105alignment:       4
106legalized:       true
107tracksRegLiveness: true
108body:             |
109  bb.1.entry:
110    liveins: $a0
111
112    ; MIPS32-LABEL: name: load2_s16_to_sextLoad2_s32
113    ; MIPS32: liveins: $a0
114    ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
115    ; MIPS32: [[SEXTLOAD:%[0-9]+]]:gprb(s32) = G_SEXTLOAD [[COPY]](p0) :: (load 2 from %ir.px)
116    ; MIPS32: $v0 = COPY [[SEXTLOAD]](s32)
117    ; MIPS32: RetRA implicit $v0
118    %0:_(p0) = COPY $a0
119    %2:_(s32) = G_SEXTLOAD %0(p0) :: (load 2 from %ir.px)
120    $v0 = COPY %2(s32)
121    RetRA implicit $v0
122
123...
124---
125name:            load4_s32_to_sextLoad4_s64
126alignment:       4
127legalized:       true
128tracksRegLiveness: true
129body:             |
130  bb.1.entry:
131    liveins: $a0
132
133    ; MIPS32-LABEL: name: load4_s32_to_sextLoad4_s64
134    ; MIPS32: liveins: $a0
135    ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
136    ; MIPS32: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.px)
137    ; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 31
138    ; MIPS32: [[C1:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0
139    ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY [[C]](s32)
140    ; MIPS32: [[ASHR:%[0-9]+]]:gprb(s32) = G_ASHR [[LOAD]], [[COPY1]](s32)
141    ; MIPS32: $v0 = COPY [[LOAD]](s32)
142    ; MIPS32: $v1 = COPY [[ASHR]](s32)
143    ; MIPS32: RetRA implicit $v0, implicit $v1
144    %0:_(p0) = COPY $a0
145    %5:_(s32) = G_LOAD %0(p0) :: (load 4 from %ir.px)
146    %9:_(s32) = G_CONSTANT i32 31
147    %10:_(s32) = G_CONSTANT i32 0
148    %8:_(s32) = COPY %9(s32)
149    %7:_(s32) = G_ASHR %5, %8(s32)
150    %2:_(s64) = G_MERGE_VALUES %5(s32), %7(s32)
151    %3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
152    $v0 = COPY %3(s32)
153    $v1 = COPY %4(s32)
154    RetRA implicit $v0, implicit $v1
155
156...
157
158