1; Test the MSA floating point conversion intrinsics (e.g. float->double) that
2; are encoded with the 2RF instruction format.
3
4; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
5; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
6
7@llvm_mips_fexupl_w_ARG1 = global <8 x half> <half 0.000000e+00, half 1.000000e+00, half 2.000000e+00, half 3.000000e+00, half 4.000000e+00, half 5.000000e+00, half 6.000000e+00, half 7.000000e+00>, align 16
8@llvm_mips_fexupl_w_RES  = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16
9
10define void @llvm_mips_fexupl_w_test() nounwind {
11entry:
12  %0 = load <8 x half>, <8 x half>* @llvm_mips_fexupl_w_ARG1
13  %1 = tail call <4 x float> @llvm.mips.fexupl.w(<8 x half> %0)
14  store <4 x float> %1, <4 x float>* @llvm_mips_fexupl_w_RES
15  ret void
16}
17
18declare <4 x float> @llvm.mips.fexupl.w(<8 x half>) nounwind
19
20; CHECK: llvm_mips_fexupl_w_test:
21; CHECK: ld.h
22; CHECK: fexupl.w
23; CHECK: st.w
24; CHECK: .size llvm_mips_fexupl_w_test
25;
26@llvm_mips_fexupl_d_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
27@llvm_mips_fexupl_d_RES  = global <2 x double> <double 0.000000e+00, double 0.000000e+00>, align 16
28
29define void @llvm_mips_fexupl_d_test() nounwind {
30entry:
31  %0 = load <4 x float>, <4 x float>* @llvm_mips_fexupl_d_ARG1
32  %1 = tail call <2 x double> @llvm.mips.fexupl.d(<4 x float> %0)
33  store <2 x double> %1, <2 x double>* @llvm_mips_fexupl_d_RES
34  ret void
35}
36
37declare <2 x double> @llvm.mips.fexupl.d(<4 x float>) nounwind
38
39; CHECK: llvm_mips_fexupl_d_test:
40; CHECK: ld.w
41; CHECK: fexupl.d
42; CHECK: st.d
43; CHECK: .size llvm_mips_fexupl_d_test
44;
45@llvm_mips_fexupr_w_ARG1 = global <8 x half> <half 0.000000e+00, half 1.000000e+00, half 2.000000e+00, half 3.000000e+00, half 4.000000e+00, half 5.000000e+00, half 6.000000e+00, half 7.000000e+00>, align 16
46@llvm_mips_fexupr_w_RES  = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16
47
48define void @llvm_mips_fexupr_w_test() nounwind {
49entry:
50  %0 = load <8 x half>, <8 x half>* @llvm_mips_fexupr_w_ARG1
51  %1 = tail call <4 x float> @llvm.mips.fexupr.w(<8 x half> %0)
52  store <4 x float> %1, <4 x float>* @llvm_mips_fexupr_w_RES
53  ret void
54}
55
56declare <4 x float> @llvm.mips.fexupr.w(<8 x half>) nounwind
57
58; CHECK: llvm_mips_fexupr_w_test:
59; CHECK: ld.h
60; CHECK: fexupr.w
61; CHECK: st.w
62; CHECK: .size llvm_mips_fexupr_w_test
63;
64@llvm_mips_fexupr_d_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
65@llvm_mips_fexupr_d_RES  = global <2 x double> <double 0.000000e+00, double 0.000000e+00>, align 16
66
67define void @llvm_mips_fexupr_d_test() nounwind {
68entry:
69  %0 = load <4 x float>, <4 x float>* @llvm_mips_fexupr_d_ARG1
70  %1 = tail call <2 x double> @llvm.mips.fexupr.d(<4 x float> %0)
71  store <2 x double> %1, <2 x double>* @llvm_mips_fexupr_d_RES
72  ret void
73}
74
75declare <2 x double> @llvm.mips.fexupr.d(<4 x float>) nounwind
76
77; CHECK: llvm_mips_fexupr_d_test:
78; CHECK: ld.w
79; CHECK: fexupr.d
80; CHECK: st.d
81; CHECK: .size llvm_mips_fexupr_d_test
82;
83