1; Test the MSA intrinsics that are encoded with the 3R instruction format and
2; use the result as a third operand.
3
4; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
5; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
6
7@llvm_mips_maddv_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
8@llvm_mips_maddv_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
9@llvm_mips_maddv_b_ARG3 = global <16 x i8> <i8 32, i8 33, i8 34, i8 35, i8 36, i8 37, i8 38, i8 39, i8 40, i8 41, i8 42, i8 43, i8 44, i8 45, i8 46, i8 47>, align 16
10@llvm_mips_maddv_b_RES  = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
11
12define void @llvm_mips_maddv_b_test() nounwind {
13entry:
14  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_maddv_b_ARG1
15  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_maddv_b_ARG2
16  %2 = load <16 x i8>, <16 x i8>* @llvm_mips_maddv_b_ARG3
17  %3 = tail call <16 x i8> @llvm.mips.maddv.b(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2)
18  store <16 x i8> %3, <16 x i8>* @llvm_mips_maddv_b_RES
19  ret void
20}
21
22declare <16 x i8> @llvm.mips.maddv.b(<16 x i8>, <16 x i8>, <16 x i8>) nounwind
23
24; CHECK: llvm_mips_maddv_b_test:
25; CHECK: ld.b
26; CHECK: ld.b
27; CHECK: ld.b
28; CHECK: maddv.b
29; CHECK: st.b
30; CHECK: .size llvm_mips_maddv_b_test
31;
32@llvm_mips_maddv_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
33@llvm_mips_maddv_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
34@llvm_mips_maddv_h_ARG3 = global <8 x i16> <i16 16, i16 17, i16 18, i16 19, i16 20, i16 21, i16 22, i16 23>, align 16
35@llvm_mips_maddv_h_RES  = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
36
37define void @llvm_mips_maddv_h_test() nounwind {
38entry:
39  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_maddv_h_ARG1
40  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_maddv_h_ARG2
41  %2 = load <8 x i16>, <8 x i16>* @llvm_mips_maddv_h_ARG3
42  %3 = tail call <8 x i16> @llvm.mips.maddv.h(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2)
43  store <8 x i16> %3, <8 x i16>* @llvm_mips_maddv_h_RES
44  ret void
45}
46
47declare <8 x i16> @llvm.mips.maddv.h(<8 x i16>, <8 x i16>, <8 x i16>) nounwind
48
49; CHECK: llvm_mips_maddv_h_test:
50; CHECK: ld.h
51; CHECK: ld.h
52; CHECK: ld.h
53; CHECK: maddv.h
54; CHECK: st.h
55; CHECK: .size llvm_mips_maddv_h_test
56;
57@llvm_mips_maddv_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
58@llvm_mips_maddv_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
59@llvm_mips_maddv_w_ARG3 = global <4 x i32> <i32 8, i32 9, i32 10, i32 11>, align 16
60@llvm_mips_maddv_w_RES  = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
61
62define void @llvm_mips_maddv_w_test() nounwind {
63entry:
64  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_maddv_w_ARG1
65  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_maddv_w_ARG2
66  %2 = load <4 x i32>, <4 x i32>* @llvm_mips_maddv_w_ARG3
67  %3 = tail call <4 x i32> @llvm.mips.maddv.w(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2)
68  store <4 x i32> %3, <4 x i32>* @llvm_mips_maddv_w_RES
69  ret void
70}
71
72declare <4 x i32> @llvm.mips.maddv.w(<4 x i32>, <4 x i32>, <4 x i32>) nounwind
73
74; CHECK: llvm_mips_maddv_w_test:
75; CHECK: ld.w
76; CHECK: ld.w
77; CHECK: ld.w
78; CHECK: maddv.w
79; CHECK: st.w
80; CHECK: .size llvm_mips_maddv_w_test
81;
82@llvm_mips_maddv_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
83@llvm_mips_maddv_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16
84@llvm_mips_maddv_d_ARG3 = global <2 x i64> <i64 4, i64 5>, align 16
85@llvm_mips_maddv_d_RES  = global <2 x i64> <i64 0, i64 0>, align 16
86
87define void @llvm_mips_maddv_d_test() nounwind {
88entry:
89  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_maddv_d_ARG1
90  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_maddv_d_ARG2
91  %2 = load <2 x i64>, <2 x i64>* @llvm_mips_maddv_d_ARG3
92  %3 = tail call <2 x i64> @llvm.mips.maddv.d(<2 x i64> %0, <2 x i64> %1, <2 x i64> %2)
93  store <2 x i64> %3, <2 x i64>* @llvm_mips_maddv_d_RES
94  ret void
95}
96
97declare <2 x i64> @llvm.mips.maddv.d(<2 x i64>, <2 x i64>, <2 x i64>) nounwind
98
99; CHECK: llvm_mips_maddv_d_test:
100; CHECK: ld.d
101; CHECK: ld.d
102; CHECK: ld.d
103; CHECK: maddv.d
104; CHECK: st.d
105; CHECK: .size llvm_mips_maddv_d_test
106;
107@llvm_mips_msubv_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
108@llvm_mips_msubv_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
109@llvm_mips_msubv_b_ARG3 = global <16 x i8> <i8 32, i8 33, i8 34, i8 35, i8 36, i8 37, i8 38, i8 39, i8 40, i8 41, i8 42, i8 43, i8 44, i8 45, i8 46, i8 47>, align 16
110@llvm_mips_msubv_b_RES  = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
111
112define void @llvm_mips_msubv_b_test() nounwind {
113entry:
114  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_msubv_b_ARG1
115  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_msubv_b_ARG2
116  %2 = load <16 x i8>, <16 x i8>* @llvm_mips_msubv_b_ARG3
117  %3 = tail call <16 x i8> @llvm.mips.msubv.b(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2)
118  store <16 x i8> %3, <16 x i8>* @llvm_mips_msubv_b_RES
119  ret void
120}
121
122declare <16 x i8> @llvm.mips.msubv.b(<16 x i8>, <16 x i8>, <16 x i8>) nounwind
123
124; CHECK: llvm_mips_msubv_b_test:
125; CHECK: ld.b
126; CHECK: ld.b
127; CHECK: ld.b
128; CHECK: msubv.b
129; CHECK: st.b
130; CHECK: .size llvm_mips_msubv_b_test
131;
132@llvm_mips_msubv_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
133@llvm_mips_msubv_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
134@llvm_mips_msubv_h_ARG3 = global <8 x i16> <i16 16, i16 17, i16 18, i16 19, i16 20, i16 21, i16 22, i16 23>, align 16
135@llvm_mips_msubv_h_RES  = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
136
137define void @llvm_mips_msubv_h_test() nounwind {
138entry:
139  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_msubv_h_ARG1
140  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_msubv_h_ARG2
141  %2 = load <8 x i16>, <8 x i16>* @llvm_mips_msubv_h_ARG3
142  %3 = tail call <8 x i16> @llvm.mips.msubv.h(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2)
143  store <8 x i16> %3, <8 x i16>* @llvm_mips_msubv_h_RES
144  ret void
145}
146
147declare <8 x i16> @llvm.mips.msubv.h(<8 x i16>, <8 x i16>, <8 x i16>) nounwind
148
149; CHECK: llvm_mips_msubv_h_test:
150; CHECK: ld.h
151; CHECK: ld.h
152; CHECK: ld.h
153; CHECK: msubv.h
154; CHECK: st.h
155; CHECK: .size llvm_mips_msubv_h_test
156;
157@llvm_mips_msubv_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
158@llvm_mips_msubv_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
159@llvm_mips_msubv_w_ARG3 = global <4 x i32> <i32 8, i32 9, i32 10, i32 11>, align 16
160@llvm_mips_msubv_w_RES  = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
161
162define void @llvm_mips_msubv_w_test() nounwind {
163entry:
164  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_msubv_w_ARG1
165  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_msubv_w_ARG2
166  %2 = load <4 x i32>, <4 x i32>* @llvm_mips_msubv_w_ARG3
167  %3 = tail call <4 x i32> @llvm.mips.msubv.w(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2)
168  store <4 x i32> %3, <4 x i32>* @llvm_mips_msubv_w_RES
169  ret void
170}
171
172declare <4 x i32> @llvm.mips.msubv.w(<4 x i32>, <4 x i32>, <4 x i32>) nounwind
173
174; CHECK: llvm_mips_msubv_w_test:
175; CHECK: ld.w
176; CHECK: ld.w
177; CHECK: ld.w
178; CHECK: msubv.w
179; CHECK: st.w
180; CHECK: .size llvm_mips_msubv_w_test
181;
182@llvm_mips_msubv_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
183@llvm_mips_msubv_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16
184@llvm_mips_msubv_d_ARG3 = global <2 x i64> <i64 4, i64 5>, align 16
185@llvm_mips_msubv_d_RES  = global <2 x i64> <i64 0, i64 0>, align 16
186
187define void @llvm_mips_msubv_d_test() nounwind {
188entry:
189  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_msubv_d_ARG1
190  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_msubv_d_ARG2
191  %2 = load <2 x i64>, <2 x i64>* @llvm_mips_msubv_d_ARG3
192  %3 = tail call <2 x i64> @llvm.mips.msubv.d(<2 x i64> %0, <2 x i64> %1, <2 x i64> %2)
193  store <2 x i64> %3, <2 x i64>* @llvm_mips_msubv_d_RES
194  ret void
195}
196
197declare <2 x i64> @llvm.mips.msubv.d(<2 x i64>, <2 x i64>, <2 x i64>) nounwind
198
199; CHECK: llvm_mips_msubv_d_test:
200; CHECK: ld.d
201; CHECK: ld.d
202; CHECK: ld.d
203; CHECK: msubv.d
204; CHECK: st.d
205; CHECK: .size llvm_mips_msubv_d_test
206;
207