1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s --check-prefixes=ALL,MIPS
3; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s --check-prefixes=ALL,MIPSEL
4
5define void @add_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
6; ALL-LABEL: add_v16i8:
7; ALL:       # %bb.0:
8; ALL-NEXT:    ld.b $w0, 0($6)
9; ALL-NEXT:    ld.b $w1, 0($5)
10; ALL-NEXT:    addv.b $w0, $w1, $w0
11; ALL-NEXT:    jr $ra
12; ALL-NEXT:    st.b $w0, 0($4)
13  %1 = load <16 x i8>, <16 x i8>* %a
14  %2 = load <16 x i8>, <16 x i8>* %b
15  %3 = add <16 x i8> %1, %2
16  store <16 x i8> %3, <16 x i8>* %c
17  ret void
18}
19
20define void @add_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
21; ALL-LABEL: add_v8i16:
22; ALL:       # %bb.0:
23; ALL-NEXT:    ld.h $w0, 0($6)
24; ALL-NEXT:    ld.h $w1, 0($5)
25; ALL-NEXT:    addv.h $w0, $w1, $w0
26; ALL-NEXT:    jr $ra
27; ALL-NEXT:    st.h $w0, 0($4)
28  %1 = load <8 x i16>, <8 x i16>* %a
29  %2 = load <8 x i16>, <8 x i16>* %b
30  %3 = add <8 x i16> %1, %2
31  store <8 x i16> %3, <8 x i16>* %c
32  ret void
33}
34
35define void @add_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
36; ALL-LABEL: add_v4i32:
37; ALL:       # %bb.0:
38; ALL-NEXT:    ld.w $w0, 0($6)
39; ALL-NEXT:    ld.w $w1, 0($5)
40; ALL-NEXT:    addv.w $w0, $w1, $w0
41; ALL-NEXT:    jr $ra
42; ALL-NEXT:    st.w $w0, 0($4)
43  %1 = load <4 x i32>, <4 x i32>* %a
44  %2 = load <4 x i32>, <4 x i32>* %b
45  %3 = add <4 x i32> %1, %2
46  store <4 x i32> %3, <4 x i32>* %c
47  ret void
48}
49
50define void @add_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
51; ALL-LABEL: add_v2i64:
52; ALL:       # %bb.0:
53; ALL-NEXT:    ld.d $w0, 0($6)
54; ALL-NEXT:    ld.d $w1, 0($5)
55; ALL-NEXT:    addv.d $w0, $w1, $w0
56; ALL-NEXT:    jr $ra
57; ALL-NEXT:    st.d $w0, 0($4)
58  %1 = load <2 x i64>, <2 x i64>* %a
59  %2 = load <2 x i64>, <2 x i64>* %b
60  %3 = add <2 x i64> %1, %2
61  store <2 x i64> %3, <2 x i64>* %c
62  ret void
63}
64
65define void @add_v16i8_i(<16 x i8>* %c, <16 x i8>* %a) nounwind {
66; ALL-LABEL: add_v16i8_i:
67; ALL:       # %bb.0:
68; ALL-NEXT:    ld.b $w0, 0($5)
69; ALL-NEXT:    addvi.b $w0, $w0, 1
70; ALL-NEXT:    jr $ra
71; ALL-NEXT:    st.b $w0, 0($4)
72  %1 = load <16 x i8>, <16 x i8>* %a
73  %2 = add <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1,
74              i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
75  store <16 x i8> %2, <16 x i8>* %c
76  ret void
77}
78
79define void @add_v8i16_i(<8 x i16>* %c, <8 x i16>* %a) nounwind {
80; ALL-LABEL: add_v8i16_i:
81; ALL:       # %bb.0:
82; ALL-NEXT:    ld.h $w0, 0($5)
83; ALL-NEXT:    addvi.h $w0, $w0, 1
84; ALL-NEXT:    jr $ra
85; ALL-NEXT:    st.h $w0, 0($4)
86  %1 = load <8 x i16>, <8 x i16>* %a
87  %2 = add <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1,
88              i16 1, i16 1, i16 1, i16 1>
89  store <8 x i16> %2, <8 x i16>* %c
90  ret void
91}
92
93define void @add_v4i32_i(<4 x i32>* %c, <4 x i32>* %a) nounwind {
94; ALL-LABEL: add_v4i32_i:
95; ALL:       # %bb.0:
96; ALL-NEXT:    ld.w $w0, 0($5)
97; ALL-NEXT:    addvi.w $w0, $w0, 1
98; ALL-NEXT:    jr $ra
99; ALL-NEXT:    st.w $w0, 0($4)
100  %1 = load <4 x i32>, <4 x i32>* %a
101  %2 = add <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
102  store <4 x i32> %2, <4 x i32>* %c
103  ret void
104}
105
106define void @add_v2i64_i(<2 x i64>* %c, <2 x i64>* %a) nounwind {
107; ALL-LABEL: add_v2i64_i:
108; ALL:       # %bb.0:
109; ALL-NEXT:    ld.d $w0, 0($5)
110; ALL-NEXT:    addvi.d $w0, $w0, 1
111; ALL-NEXT:    jr $ra
112; ALL-NEXT:    st.d $w0, 0($4)
113  %1 = load <2 x i64>, <2 x i64>* %a
114  %2 = add <2 x i64> %1, <i64 1, i64 1>
115  store <2 x i64> %2, <2 x i64>* %c
116  ret void
117}
118
119define void @sub_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
120; ALL-LABEL: sub_v16i8:
121; ALL:       # %bb.0:
122; ALL-NEXT:    ld.b $w0, 0($6)
123; ALL-NEXT:    ld.b $w1, 0($5)
124; ALL-NEXT:    subv.b $w0, $w1, $w0
125; ALL-NEXT:    jr $ra
126; ALL-NEXT:    st.b $w0, 0($4)
127  %1 = load <16 x i8>, <16 x i8>* %a
128  %2 = load <16 x i8>, <16 x i8>* %b
129  %3 = sub <16 x i8> %1, %2
130  store <16 x i8> %3, <16 x i8>* %c
131  ret void
132}
133
134define void @sub_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
135; ALL-LABEL: sub_v8i16:
136; ALL:       # %bb.0:
137; ALL-NEXT:    ld.h $w0, 0($6)
138; ALL-NEXT:    ld.h $w1, 0($5)
139; ALL-NEXT:    subv.h $w0, $w1, $w0
140; ALL-NEXT:    jr $ra
141; ALL-NEXT:    st.h $w0, 0($4)
142  %1 = load <8 x i16>, <8 x i16>* %a
143  %2 = load <8 x i16>, <8 x i16>* %b
144  %3 = sub <8 x i16> %1, %2
145  store <8 x i16> %3, <8 x i16>* %c
146  ret void
147}
148
149define void @sub_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
150; ALL-LABEL: sub_v4i32:
151; ALL:       # %bb.0:
152; ALL-NEXT:    ld.w $w0, 0($6)
153; ALL-NEXT:    ld.w $w1, 0($5)
154; ALL-NEXT:    subv.w $w0, $w1, $w0
155; ALL-NEXT:    jr $ra
156; ALL-NEXT:    st.w $w0, 0($4)
157  %1 = load <4 x i32>, <4 x i32>* %a
158  %2 = load <4 x i32>, <4 x i32>* %b
159  %3 = sub <4 x i32> %1, %2
160  store <4 x i32> %3, <4 x i32>* %c
161  ret void
162}
163
164define void @sub_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
165; ALL-LABEL: sub_v2i64:
166; ALL:       # %bb.0:
167; ALL-NEXT:    ld.d $w0, 0($6)
168; ALL-NEXT:    ld.d $w1, 0($5)
169; ALL-NEXT:    subv.d $w0, $w1, $w0
170; ALL-NEXT:    jr $ra
171; ALL-NEXT:    st.d $w0, 0($4)
172  %1 = load <2 x i64>, <2 x i64>* %a
173  %2 = load <2 x i64>, <2 x i64>* %b
174  %3 = sub <2 x i64> %1, %2
175  store <2 x i64> %3, <2 x i64>* %c
176  ret void
177}
178
179define void @sub_v16i8_i(<16 x i8>* %c, <16 x i8>* %a) nounwind {
180; ALL-LABEL: sub_v16i8_i:
181; ALL:       # %bb.0:
182; ALL-NEXT:    ld.b $w0, 0($5)
183; ALL-NEXT:    subvi.b $w0, $w0, 1
184; ALL-NEXT:    jr $ra
185; ALL-NEXT:    st.b $w0, 0($4)
186  %1 = load <16 x i8>, <16 x i8>* %a
187  %2 = sub <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1,
188              i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
189  store <16 x i8> %2, <16 x i8>* %c
190  ret void
191}
192
193define void @sub_v16i8_i_negated(<16 x i8>* %c, <16 x i8>* %a) nounwind {
194; ALL-LABEL: sub_v16i8_i_negated:
195; ALL:       # %bb.0:
196; ALL-NEXT:    ld.b $w0, 0($5)
197; ALL-NEXT:    subvi.b $w0, $w0, 1
198; ALL-NEXT:    jr $ra
199; ALL-NEXT:    st.b $w0, 0($4)
200  %1 = load <16 x i8>, <16 x i8>* %a
201  %2 = add <16 x i8> %1, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1,
202              i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
203  store <16 x i8> %2, <16 x i8>* %c
204  ret void
205}
206
207define void @sub_v8i16_i(<8 x i16>* %c, <8 x i16>* %a) nounwind {
208; ALL-LABEL: sub_v8i16_i:
209; ALL:       # %bb.0:
210; ALL-NEXT:    ld.h $w0, 0($5)
211; ALL-NEXT:    subvi.h $w0, $w0, 1
212; ALL-NEXT:    jr $ra
213; ALL-NEXT:    st.h $w0, 0($4)
214  %1 = load <8 x i16>, <8 x i16>* %a
215  %2 = sub <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1,
216              i16 1, i16 1, i16 1, i16 1>
217  store <8 x i16> %2, <8 x i16>* %c
218  ret void
219}
220
221define void @sub_v8i16_i_negated(<8 x i16>* %c, <8 x i16>* %a) nounwind {
222; ALL-LABEL: sub_v8i16_i_negated:
223; ALL:       # %bb.0:
224; ALL-NEXT:    ld.h $w0, 0($5)
225; ALL-NEXT:    subvi.h $w0, $w0, 1
226; ALL-NEXT:    jr $ra
227; ALL-NEXT:    st.h $w0, 0($4)
228  %1 = load <8 x i16>, <8 x i16>* %a
229  %2 = add <8 x i16> %1, <i16 -1, i16 -1, i16 -1, i16 -1,
230              i16 -1, i16 -1, i16 -1, i16 -1>
231  store <8 x i16> %2, <8 x i16>* %c
232  ret void
233}
234
235define void @sub_v4i32_i(<4 x i32>* %c, <4 x i32>* %a) nounwind {
236; ALL-LABEL: sub_v4i32_i:
237; ALL:       # %bb.0:
238; ALL-NEXT:    ld.w $w0, 0($5)
239; ALL-NEXT:    subvi.w $w0, $w0, 1
240; ALL-NEXT:    jr $ra
241; ALL-NEXT:    st.w $w0, 0($4)
242  %1 = load <4 x i32>, <4 x i32>* %a
243  %2 = sub <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
244  store <4 x i32> %2, <4 x i32>* %c
245  ret void
246}
247
248define void @sub_v4i32_i_negated(<4 x i32>* %c, <4 x i32>* %a) nounwind {
249; ALL-LABEL: sub_v4i32_i_negated:
250; ALL:       # %bb.0:
251; ALL-NEXT:    ld.w $w0, 0($5)
252; ALL-NEXT:    subvi.w $w0, $w0, 1
253; ALL-NEXT:    jr $ra
254; ALL-NEXT:    st.w $w0, 0($4)
255  %1 = load <4 x i32>, <4 x i32>* %a
256  %2 = add <4 x i32> %1, <i32 -1, i32 -1, i32 -1, i32 -1>
257  store <4 x i32> %2, <4 x i32>* %c
258  ret void
259}
260
261define void @sub_v2i64_i(<2 x i64>* %c, <2 x i64>* %a) nounwind {
262; ALL-LABEL: sub_v2i64_i:
263; ALL:       # %bb.0:
264; ALL-NEXT:    ld.d $w0, 0($5)
265; ALL-NEXT:    subvi.d $w0, $w0, 1
266; ALL-NEXT:    jr $ra
267; ALL-NEXT:    st.d $w0, 0($4)
268  %1 = load <2 x i64>, <2 x i64>* %a
269  %2 = sub <2 x i64> %1, <i64 1, i64 1>
270  store <2 x i64> %2, <2 x i64>* %c
271  ret void
272}
273
274define void @sub_v2i64_i_negated(<2 x i64>* %c, <2 x i64>* %a) nounwind {
275; MIPS-LABEL: sub_v2i64_i_negated:
276; MIPS:       # %bb.0:
277; MIPS-NEXT:    ldi.b $w0, -1
278; MIPS-NEXT:    shf.w $w0, $w0, 177
279; MIPS-NEXT:    ld.d $w1, 0($5)
280; MIPS-NEXT:    addv.d $w0, $w1, $w0
281; MIPS-NEXT:    jr $ra
282; MIPS-NEXT:    st.d $w0, 0($4)
283;
284; MIPSEL-LABEL: sub_v2i64_i_negated:
285; MIPSEL:       # %bb.0:
286; MIPSEL-NEXT:    ldi.b $w0, -1
287; MIPSEL-NEXT:    ld.d $w1, 0($5)
288; MIPSEL-NEXT:    addv.d $w0, $w1, $w0
289; MIPSEL-NEXT:    jr $ra
290; MIPSEL-NEXT:    st.d $w0, 0($4)
291  %1 = load <2 x i64>, <2 x i64>* %a
292  %2 = add <2 x i64> %1, <i64 -1, i64 -1>
293  store <2 x i64> %2, <2 x i64>* %c
294  ret void
295}
296
297define void @mul_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
298; ALL-LABEL: mul_v16i8:
299; ALL:       # %bb.0:
300; ALL-NEXT:    ld.b $w0, 0($6)
301; ALL-NEXT:    ld.b $w1, 0($5)
302; ALL-NEXT:    mulv.b $w0, $w1, $w0
303; ALL-NEXT:    jr $ra
304; ALL-NEXT:    st.b $w0, 0($4)
305  %1 = load <16 x i8>, <16 x i8>* %a
306  %2 = load <16 x i8>, <16 x i8>* %b
307  %3 = mul <16 x i8> %1, %2
308  store <16 x i8> %3, <16 x i8>* %c
309  ret void
310}
311
312define void @mul_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
313; ALL-LABEL: mul_v8i16:
314; ALL:       # %bb.0:
315; ALL-NEXT:    ld.h $w0, 0($6)
316; ALL-NEXT:    ld.h $w1, 0($5)
317; ALL-NEXT:    mulv.h $w0, $w1, $w0
318; ALL-NEXT:    jr $ra
319; ALL-NEXT:    st.h $w0, 0($4)
320  %1 = load <8 x i16>, <8 x i16>* %a
321  %2 = load <8 x i16>, <8 x i16>* %b
322  %3 = mul <8 x i16> %1, %2
323  store <8 x i16> %3, <8 x i16>* %c
324  ret void
325}
326
327define void @mul_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
328; ALL-LABEL: mul_v4i32:
329; ALL:       # %bb.0:
330; ALL-NEXT:    ld.w $w0, 0($6)
331; ALL-NEXT:    ld.w $w1, 0($5)
332; ALL-NEXT:    mulv.w $w0, $w1, $w0
333; ALL-NEXT:    jr $ra
334; ALL-NEXT:    st.w $w0, 0($4)
335  %1 = load <4 x i32>, <4 x i32>* %a
336  %2 = load <4 x i32>, <4 x i32>* %b
337  %3 = mul <4 x i32> %1, %2
338  store <4 x i32> %3, <4 x i32>* %c
339  ret void
340}
341
342define void @mul_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
343; ALL-LABEL: mul_v2i64:
344; ALL:       # %bb.0:
345; ALL-NEXT:    ld.d $w0, 0($6)
346; ALL-NEXT:    ld.d $w1, 0($5)
347; ALL-NEXT:    mulv.d $w0, $w1, $w0
348; ALL-NEXT:    jr $ra
349; ALL-NEXT:    st.d $w0, 0($4)
350  %1 = load <2 x i64>, <2 x i64>* %a
351  %2 = load <2 x i64>, <2 x i64>* %b
352  %3 = mul <2 x i64> %1, %2
353  store <2 x i64> %3, <2 x i64>* %c
354  ret void
355}
356
357define void @maddv_v16i8(<16 x i8>* %d, <16 x i8>* %a, <16 x i8>* %b,
358; ALL-LABEL: maddv_v16i8:
359; ALL:       # %bb.0:
360; ALL-NEXT:    ld.b $w0, 0($7)
361; ALL-NEXT:    ld.b $w1, 0($6)
362; ALL-NEXT:    ld.b $w2, 0($5)
363; ALL-NEXT:    maddv.b $w2, $w1, $w0
364; ALL-NEXT:    jr $ra
365; ALL-NEXT:    st.b $w2, 0($4)
366             <16 x i8>* %c) nounwind {
367  %1 = load <16 x i8>, <16 x i8>* %a
368  %2 = load <16 x i8>, <16 x i8>* %b
369  %3 = load <16 x i8>, <16 x i8>* %c
370  %4 = mul <16 x i8> %2, %3
371  %5 = add <16 x i8> %4, %1
372  store <16 x i8> %5, <16 x i8>* %d
373  ret void
374}
375
376define void @maddv_v8i16(<8 x i16>* %d, <8 x i16>* %a, <8 x i16>* %b,
377; ALL-LABEL: maddv_v8i16:
378; ALL:       # %bb.0:
379; ALL-NEXT:    ld.h $w0, 0($7)
380; ALL-NEXT:    ld.h $w1, 0($6)
381; ALL-NEXT:    ld.h $w2, 0($5)
382; ALL-NEXT:    maddv.h $w2, $w1, $w0
383; ALL-NEXT:    jr $ra
384; ALL-NEXT:    st.h $w2, 0($4)
385             <8 x i16>* %c) nounwind {
386  %1 = load <8 x i16>, <8 x i16>* %a
387  %2 = load <8 x i16>, <8 x i16>* %b
388  %3 = load <8 x i16>, <8 x i16>* %c
389  %4 = mul <8 x i16> %2, %3
390  %5 = add <8 x i16> %4, %1
391  store <8 x i16> %5, <8 x i16>* %d
392  ret void
393}
394
395define void @maddv_v4i32(<4 x i32>* %d, <4 x i32>* %a, <4 x i32>* %b,
396; ALL-LABEL: maddv_v4i32:
397; ALL:       # %bb.0:
398; ALL-NEXT:    ld.w $w0, 0($7)
399; ALL-NEXT:    ld.w $w1, 0($6)
400; ALL-NEXT:    ld.w $w2, 0($5)
401; ALL-NEXT:    maddv.w $w2, $w1, $w0
402; ALL-NEXT:    jr $ra
403; ALL-NEXT:    st.w $w2, 0($4)
404             <4 x i32>* %c) nounwind {
405  %1 = load <4 x i32>, <4 x i32>* %a
406  %2 = load <4 x i32>, <4 x i32>* %b
407  %3 = load <4 x i32>, <4 x i32>* %c
408  %4 = mul <4 x i32> %2, %3
409  %5 = add <4 x i32> %4, %1
410  store <4 x i32> %5, <4 x i32>* %d
411  ret void
412}
413
414define void @maddv_v2i64(<2 x i64>* %d, <2 x i64>* %a, <2 x i64>* %b,
415; ALL-LABEL: maddv_v2i64:
416; ALL:       # %bb.0:
417; ALL-NEXT:    ld.d $w0, 0($7)
418; ALL-NEXT:    ld.d $w1, 0($6)
419; ALL-NEXT:    ld.d $w2, 0($5)
420; ALL-NEXT:    maddv.d $w2, $w1, $w0
421; ALL-NEXT:    jr $ra
422; ALL-NEXT:    st.d $w2, 0($4)
423             <2 x i64>* %c) nounwind {
424  %1 = load <2 x i64>, <2 x i64>* %a
425  %2 = load <2 x i64>, <2 x i64>* %b
426  %3 = load <2 x i64>, <2 x i64>* %c
427  %4 = mul <2 x i64> %2, %3
428  %5 = add <2 x i64> %4, %1
429  store <2 x i64> %5, <2 x i64>* %d
430  ret void
431}
432
433define void @msubv_v16i8(<16 x i8>* %d, <16 x i8>* %a, <16 x i8>* %b,
434; ALL-LABEL: msubv_v16i8:
435; ALL:       # %bb.0:
436; ALL-NEXT:    ld.b $w0, 0($7)
437; ALL-NEXT:    ld.b $w1, 0($6)
438; ALL-NEXT:    ld.b $w2, 0($5)
439; ALL-NEXT:    msubv.b $w2, $w1, $w0
440; ALL-NEXT:    jr $ra
441; ALL-NEXT:    st.b $w2, 0($4)
442             <16 x i8>* %c) nounwind {
443  %1 = load <16 x i8>, <16 x i8>* %a
444  %2 = load <16 x i8>, <16 x i8>* %b
445  %3 = load <16 x i8>, <16 x i8>* %c
446  %4 = mul <16 x i8> %2, %3
447  %5 = sub <16 x i8> %1, %4
448  store <16 x i8> %5, <16 x i8>* %d
449  ret void
450}
451
452define void @msubv_v8i16(<8 x i16>* %d, <8 x i16>* %a, <8 x i16>* %b,
453; ALL-LABEL: msubv_v8i16:
454; ALL:       # %bb.0:
455; ALL-NEXT:    ld.h $w0, 0($7)
456; ALL-NEXT:    ld.h $w1, 0($6)
457; ALL-NEXT:    ld.h $w2, 0($5)
458; ALL-NEXT:    msubv.h $w2, $w1, $w0
459; ALL-NEXT:    jr $ra
460; ALL-NEXT:    st.h $w2, 0($4)
461             <8 x i16>* %c) nounwind {
462  %1 = load <8 x i16>, <8 x i16>* %a
463  %2 = load <8 x i16>, <8 x i16>* %b
464  %3 = load <8 x i16>, <8 x i16>* %c
465  %4 = mul <8 x i16> %2, %3
466  %5 = sub <8 x i16> %1, %4
467  store <8 x i16> %5, <8 x i16>* %d
468  ret void
469}
470
471define void @msubv_v4i32(<4 x i32>* %d, <4 x i32>* %a, <4 x i32>* %b,
472; ALL-LABEL: msubv_v4i32:
473; ALL:       # %bb.0:
474; ALL-NEXT:    ld.w $w0, 0($7)
475; ALL-NEXT:    ld.w $w1, 0($6)
476; ALL-NEXT:    ld.w $w2, 0($5)
477; ALL-NEXT:    msubv.w $w2, $w1, $w0
478; ALL-NEXT:    jr $ra
479; ALL-NEXT:    st.w $w2, 0($4)
480             <4 x i32>* %c) nounwind {
481  %1 = load <4 x i32>, <4 x i32>* %a
482  %2 = load <4 x i32>, <4 x i32>* %b
483  %3 = load <4 x i32>, <4 x i32>* %c
484  %4 = mul <4 x i32> %2, %3
485  %5 = sub <4 x i32> %1, %4
486  store <4 x i32> %5, <4 x i32>* %d
487  ret void
488}
489
490define void @msubv_v2i64(<2 x i64>* %d, <2 x i64>* %a, <2 x i64>* %b,
491; ALL-LABEL: msubv_v2i64:
492; ALL:       # %bb.0:
493; ALL-NEXT:    ld.d $w0, 0($7)
494; ALL-NEXT:    ld.d $w1, 0($6)
495; ALL-NEXT:    ld.d $w2, 0($5)
496; ALL-NEXT:    msubv.d $w2, $w1, $w0
497; ALL-NEXT:    jr $ra
498; ALL-NEXT:    st.d $w2, 0($4)
499             <2 x i64>* %c) nounwind {
500  %1 = load <2 x i64>, <2 x i64>* %a
501  %2 = load <2 x i64>, <2 x i64>* %b
502  %3 = load <2 x i64>, <2 x i64>* %c
503  %4 = mul <2 x i64> %2, %3
504  %5 = sub <2 x i64> %1, %4
505  store <2 x i64> %5, <2 x i64>* %d
506  ret void
507}
508
509define void @div_s_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
510; ALL-LABEL: div_s_v16i8:
511; ALL:       # %bb.0:
512; ALL-NEXT:    ld.b $w0, 0($6)
513; ALL-NEXT:    ld.b $w1, 0($5)
514; ALL-NEXT:    div_s.b $w0, $w1, $w0
515; ALL-NEXT:    jr $ra
516; ALL-NEXT:    st.b $w0, 0($4)
517  %1 = load <16 x i8>, <16 x i8>* %a
518  %2 = load <16 x i8>, <16 x i8>* %b
519  %3 = sdiv <16 x i8> %1, %2
520  store <16 x i8> %3, <16 x i8>* %c
521  ret void
522}
523
524define void @div_s_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
525; ALL-LABEL: div_s_v8i16:
526; ALL:       # %bb.0:
527; ALL-NEXT:    ld.h $w0, 0($6)
528; ALL-NEXT:    ld.h $w1, 0($5)
529; ALL-NEXT:    div_s.h $w0, $w1, $w0
530; ALL-NEXT:    jr $ra
531; ALL-NEXT:    st.h $w0, 0($4)
532  %1 = load <8 x i16>, <8 x i16>* %a
533  %2 = load <8 x i16>, <8 x i16>* %b
534  %3 = sdiv <8 x i16> %1, %2
535  store <8 x i16> %3, <8 x i16>* %c
536  ret void
537}
538
539define void @div_s_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
540; ALL-LABEL: div_s_v4i32:
541; ALL:       # %bb.0:
542; ALL-NEXT:    ld.w $w0, 0($6)
543; ALL-NEXT:    ld.w $w1, 0($5)
544; ALL-NEXT:    div_s.w $w0, $w1, $w0
545; ALL-NEXT:    jr $ra
546; ALL-NEXT:    st.w $w0, 0($4)
547  %1 = load <4 x i32>, <4 x i32>* %a
548  %2 = load <4 x i32>, <4 x i32>* %b
549  %3 = sdiv <4 x i32> %1, %2
550  store <4 x i32> %3, <4 x i32>* %c
551  ret void
552}
553
554define void @div_s_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
555; ALL-LABEL: div_s_v2i64:
556; ALL:       # %bb.0:
557; ALL-NEXT:    ld.d $w0, 0($6)
558; ALL-NEXT:    ld.d $w1, 0($5)
559; ALL-NEXT:    div_s.d $w0, $w1, $w0
560; ALL-NEXT:    jr $ra
561; ALL-NEXT:    st.d $w0, 0($4)
562  %1 = load <2 x i64>, <2 x i64>* %a
563  %2 = load <2 x i64>, <2 x i64>* %b
564  %3 = sdiv <2 x i64> %1, %2
565  store <2 x i64> %3, <2 x i64>* %c
566  ret void
567}
568
569define void @div_u_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
570; ALL-LABEL: div_u_v16i8:
571; ALL:       # %bb.0:
572; ALL-NEXT:    ld.b $w0, 0($6)
573; ALL-NEXT:    ld.b $w1, 0($5)
574; ALL-NEXT:    div_u.b $w0, $w1, $w0
575; ALL-NEXT:    jr $ra
576; ALL-NEXT:    st.b $w0, 0($4)
577  %1 = load <16 x i8>, <16 x i8>* %a
578  %2 = load <16 x i8>, <16 x i8>* %b
579  %3 = udiv <16 x i8> %1, %2
580  store <16 x i8> %3, <16 x i8>* %c
581  ret void
582}
583
584define void @div_u_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
585; ALL-LABEL: div_u_v8i16:
586; ALL:       # %bb.0:
587; ALL-NEXT:    ld.h $w0, 0($6)
588; ALL-NEXT:    ld.h $w1, 0($5)
589; ALL-NEXT:    div_u.h $w0, $w1, $w0
590; ALL-NEXT:    jr $ra
591; ALL-NEXT:    st.h $w0, 0($4)
592  %1 = load <8 x i16>, <8 x i16>* %a
593  %2 = load <8 x i16>, <8 x i16>* %b
594  %3 = udiv <8 x i16> %1, %2
595  store <8 x i16> %3, <8 x i16>* %c
596  ret void
597}
598
599define void @div_u_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
600; ALL-LABEL: div_u_v4i32:
601; ALL:       # %bb.0:
602; ALL-NEXT:    ld.w $w0, 0($6)
603; ALL-NEXT:    ld.w $w1, 0($5)
604; ALL-NEXT:    div_u.w $w0, $w1, $w0
605; ALL-NEXT:    jr $ra
606; ALL-NEXT:    st.w $w0, 0($4)
607  %1 = load <4 x i32>, <4 x i32>* %a
608  %2 = load <4 x i32>, <4 x i32>* %b
609  %3 = udiv <4 x i32> %1, %2
610  store <4 x i32> %3, <4 x i32>* %c
611  ret void
612}
613
614define void @div_u_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
615; ALL-LABEL: div_u_v2i64:
616; ALL:       # %bb.0:
617; ALL-NEXT:    ld.d $w0, 0($6)
618; ALL-NEXT:    ld.d $w1, 0($5)
619; ALL-NEXT:    div_u.d $w0, $w1, $w0
620; ALL-NEXT:    jr $ra
621; ALL-NEXT:    st.d $w0, 0($4)
622  %1 = load <2 x i64>, <2 x i64>* %a
623  %2 = load <2 x i64>, <2 x i64>* %b
624  %3 = udiv <2 x i64> %1, %2
625  store <2 x i64> %3, <2 x i64>* %c
626  ret void
627}
628
629define void @mod_s_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
630; ALL-LABEL: mod_s_v16i8:
631; ALL:       # %bb.0:
632; ALL-NEXT:    ld.b $w0, 0($6)
633; ALL-NEXT:    ld.b $w1, 0($5)
634; ALL-NEXT:    mod_s.b $w0, $w1, $w0
635; ALL-NEXT:    jr $ra
636; ALL-NEXT:    st.b $w0, 0($4)
637  %1 = load <16 x i8>, <16 x i8>* %a
638  %2 = load <16 x i8>, <16 x i8>* %b
639  %3 = srem <16 x i8> %1, %2
640  store <16 x i8> %3, <16 x i8>* %c
641  ret void
642}
643
644define void @mod_s_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
645; ALL-LABEL: mod_s_v8i16:
646; ALL:       # %bb.0:
647; ALL-NEXT:    ld.h $w0, 0($6)
648; ALL-NEXT:    ld.h $w1, 0($5)
649; ALL-NEXT:    mod_s.h $w0, $w1, $w0
650; ALL-NEXT:    jr $ra
651; ALL-NEXT:    st.h $w0, 0($4)
652  %1 = load <8 x i16>, <8 x i16>* %a
653  %2 = load <8 x i16>, <8 x i16>* %b
654  %3 = srem <8 x i16> %1, %2
655  store <8 x i16> %3, <8 x i16>* %c
656  ret void
657}
658
659define void @mod_s_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
660; ALL-LABEL: mod_s_v4i32:
661; ALL:       # %bb.0:
662; ALL-NEXT:    ld.w $w0, 0($6)
663; ALL-NEXT:    ld.w $w1, 0($5)
664; ALL-NEXT:    mod_s.w $w0, $w1, $w0
665; ALL-NEXT:    jr $ra
666; ALL-NEXT:    st.w $w0, 0($4)
667  %1 = load <4 x i32>, <4 x i32>* %a
668  %2 = load <4 x i32>, <4 x i32>* %b
669  %3 = srem <4 x i32> %1, %2
670  store <4 x i32> %3, <4 x i32>* %c
671  ret void
672}
673
674define void @mod_s_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
675; ALL-LABEL: mod_s_v2i64:
676; ALL:       # %bb.0:
677; ALL-NEXT:    ld.d $w0, 0($6)
678; ALL-NEXT:    ld.d $w1, 0($5)
679; ALL-NEXT:    mod_s.d $w0, $w1, $w0
680; ALL-NEXT:    jr $ra
681; ALL-NEXT:    st.d $w0, 0($4)
682  %1 = load <2 x i64>, <2 x i64>* %a
683  %2 = load <2 x i64>, <2 x i64>* %b
684  %3 = srem <2 x i64> %1, %2
685  store <2 x i64> %3, <2 x i64>* %c
686  ret void
687}
688
689define void @mod_u_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
690; ALL-LABEL: mod_u_v16i8:
691; ALL:       # %bb.0:
692; ALL-NEXT:    ld.b $w0, 0($6)
693; ALL-NEXT:    ld.b $w1, 0($5)
694; ALL-NEXT:    mod_u.b $w0, $w1, $w0
695; ALL-NEXT:    jr $ra
696; ALL-NEXT:    st.b $w0, 0($4)
697  %1 = load <16 x i8>, <16 x i8>* %a
698  %2 = load <16 x i8>, <16 x i8>* %b
699  %3 = urem <16 x i8> %1, %2
700  store <16 x i8> %3, <16 x i8>* %c
701  ret void
702}
703
704define void @mod_u_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
705; ALL-LABEL: mod_u_v8i16:
706; ALL:       # %bb.0:
707; ALL-NEXT:    ld.h $w0, 0($6)
708; ALL-NEXT:    ld.h $w1, 0($5)
709; ALL-NEXT:    mod_u.h $w0, $w1, $w0
710; ALL-NEXT:    jr $ra
711; ALL-NEXT:    st.h $w0, 0($4)
712  %1 = load <8 x i16>, <8 x i16>* %a
713  %2 = load <8 x i16>, <8 x i16>* %b
714  %3 = urem <8 x i16> %1, %2
715  store <8 x i16> %3, <8 x i16>* %c
716  ret void
717}
718
719define void @mod_u_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
720; ALL-LABEL: mod_u_v4i32:
721; ALL:       # %bb.0:
722; ALL-NEXT:    ld.w $w0, 0($6)
723; ALL-NEXT:    ld.w $w1, 0($5)
724; ALL-NEXT:    mod_u.w $w0, $w1, $w0
725; ALL-NEXT:    jr $ra
726; ALL-NEXT:    st.w $w0, 0($4)
727  %1 = load <4 x i32>, <4 x i32>* %a
728  %2 = load <4 x i32>, <4 x i32>* %b
729  %3 = urem <4 x i32> %1, %2
730  store <4 x i32> %3, <4 x i32>* %c
731  ret void
732}
733
734define void @mod_u_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
735; ALL-LABEL: mod_u_v2i64:
736; ALL:       # %bb.0:
737; ALL-NEXT:    ld.d $w0, 0($6)
738; ALL-NEXT:    ld.d $w1, 0($5)
739; ALL-NEXT:    mod_u.d $w0, $w1, $w0
740; ALL-NEXT:    jr $ra
741; ALL-NEXT:    st.d $w0, 0($4)
742  %1 = load <2 x i64>, <2 x i64>* %a
743  %2 = load <2 x i64>, <2 x i64>* %b
744  %3 = urem <2 x i64> %1, %2
745  store <2 x i64> %3, <2 x i64>* %c
746  ret void
747}
748