1; RUN: llc -march=mips -mcpu=mips32r5 -mattr=+msa,+fp64 -relocation-model=pic \ 2; RUN: -verify-machineinstrs < %s \ 3; RUN: | FileCheck -check-prefixes=ALL,O32,MIPS32,ALL-BE,O32-BE %s 4; RUN: llc -march=mipsel -mcpu=mips32r5 -mattr=+msa,+fp64 -relocation-model=pic \ 5; RUN: -verify-machineinstrs < %s \ 6; RUN: | FileCheck -check-prefixes=ALL,O32,MIPS32,ALL-LE,O32-LE %s 7; RUN: llc -march=mips64 -mcpu=mips64r5 -target-abi n32 -mattr=+msa,+fp64 \ 8; RUN: -relocation-model=pic -verify-machineinstrs < %s \ 9; RUN: | FileCheck -check-prefixes=ALL,N32,MIPS64,ALL-BE %s 10; RUN: llc -march=mips64el -mcpu=mips64r5 -target-abi n32 -mattr=+msa,+fp64 \ 11; RUN: -relocation-model=pic -verify-machineinstrs < %s \ 12; RUN: | FileCheck -check-prefixes=ALL,N32,MIPS64,ALL-LE %s 13; RUN: llc -march=mips64 -mcpu=mips64r5 -mattr=+msa,+fp64 -relocation-model=pic \ 14; RUN: -verify-machineinstrs < %s \ 15; RUN: | FileCheck -check-prefixes=ALL,N64,MIPS64,ALL-BE %s 16; RUN: llc -march=mips64el -mcpu=mips64r5 -mattr=+msa,+fp64 -relocation-model=pic \ 17; RUN: -verify-machineinstrs < %s \ 18; RUN: | FileCheck -check-prefixes=ALL,N64,MIPS64,ALL-LE %s 19 20@v4i8 = global <4 x i8> <i8 0, i8 0, i8 0, i8 0> 21@v16i8 = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0> 22@v8i16 = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0> 23@v4i32 = global <4 x i32> <i32 0, i32 0, i32 0, i32 0> 24@v2i64 = global <2 x i64> <i64 0, i64 0> 25@i32 = global i32 0 26@i64 = global i64 0 27 28define void @const_v16i8() nounwind { 29 ; ALL-LABEL: const_v16i8: 30 31 store volatile <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, <16 x i8>*@v16i8 32 ; ALL: ldi.b [[R1:\$w[0-9]+]], 0 33 34 store volatile <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>, <16 x i8>*@v16i8 35 ; ALL: ldi.b [[R1:\$w[0-9]+]], 1 36 37 store volatile <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 31>, <16 x i8>*@v16i8 38 ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ 39 ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L 40 ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L 41 ; ALL: ld.b [[R1:\$w[0-9]+]], 0([[G_PTR]]) 42 43 store volatile <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6>, <16 x i8>*@v16i8 44 ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ 45 ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L 46 ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L 47 ; ALL: ld.b [[R1:\$w[0-9]+]], 0([[G_PTR]]) 48 49 store volatile <16 x i8> <i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0>, <16 x i8>*@v16i8 50 ; ALL-BE: ldi.h [[R1:\$w[0-9]+]], 256 51 ; ALL-LE: ldi.h [[R1:\$w[0-9]+]], 1 52 53 store volatile <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 1, i8 2, i8 3, i8 4, i8 1, i8 2, i8 3, i8 4, i8 1, i8 2, i8 3, i8 4>, <16 x i8>*@v16i8 54 ; ALL-BE-DAG: lui [[R2:\$[0-9]+]], 258 55 ; ALL-LE-DAG: lui [[R2:\$[0-9]+]], 1027 56 ; ALL-BE-DAG: ori [[R2]], [[R2]], 772 57 ; ALL-LE-DAG: ori [[R2]], [[R2]], 513 58 ; ALL-DAG: fill.w [[R1:\$w[0-9]+]], [[R2]] 59 60 store volatile <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, <16 x i8>*@v16i8 61 ; ALL-BE-DAG: lui [[R3:\$[0-9]+]], 1286 62 ; ALL-LE-DAG: lui [[R3:\$[0-9]+]], 2055 63 ; ALL-BE-DAG: ori [[R4:\$[0-9]+]], [[R3]], 1800 64 ; ALL-LE-DAG: ori [[R4:\$[0-9]+]], [[R3]], 1541 65 ; O32-BE: fill.w [[R1:\$w[0-9]+]], [[R4]] 66 67 ; O32: insert.w [[R1]][1], [[R2]] 68 ; O32: splati.d $w{{.*}}, [[R1]][0] 69 70 ; MIPS64-BE: dinsu [[R4]], [[R2]], 32, 32 71 ; MIPS64-LE: dinsu [[R2]], [[R4]], 32, 32 72 ; MIPS64-BE: fill.d $w{{.*}}, [[R4]] 73 ; MIPS64-LE: fill.d $w{{.*}}, [[R2]] 74 75 ret void 76} 77 78define void @const_v8i16() nounwind { 79 ; ALL-LABEL: const_v8i16: 80 81 store volatile <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, <8 x i16>*@v8i16 82 ; ALL: ldi.b [[R1:\$w[0-9]+]], 0 83 84 store volatile <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>, <8 x i16>*@v8i16 85 ; ALL: ldi.h [[R1:\$w[0-9]+]], 1 86 87 store volatile <8 x i16> <i16 1, i16 1, i16 1, i16 2, i16 1, i16 1, i16 1, i16 31>, <8 x i16>*@v8i16 88 ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ 89 ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L 90 ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L 91 ; ALL: ld.h [[R1:\$w[0-9]+]], 0([[G_PTR]]) 92 93 store volatile <8 x i16> <i16 1028, i16 1028, i16 1028, i16 1028, i16 1028, i16 1028, i16 1028, i16 1028>, <8 x i16>*@v8i16 94 ; ALL: ldi.b [[R1:\$w[0-9]+]], 4 95 96 store volatile <8 x i16> <i16 1, i16 2, i16 1, i16 2, i16 1, i16 2, i16 1, i16 2>, <8 x i16>*@v8i16 97 ; ALL-BE-DAG: lui [[R2:\$[0-9]+]], 1 98 ; ALL-LE-DAG: lui [[R2:\$[0-9]+]], 2 99 ; ALL-BE-DAG: ori [[R2]], [[R2]], 2 100 ; ALL-LE-DAG: ori [[R2]], [[R2]], 1 101 ; ALL-DAG: fill.w [[R1:\$w[0-9]+]], [[R2]] 102 103 store volatile <8 x i16> <i16 1, i16 2, i16 3, i16 4, i16 1, i16 2, i16 3, i16 4>, <8 x i16>*@v8i16 104 ; ALL-BE-DAG: lui [[R3:\$[0-9]+]], 3 105 ; ALL-LE-DAG: lui [[R3:\$[0-9]+]], 4 106 ; ALL-BE-DAG: ori [[R4:\$[0-9]+]], [[R3]], 4 107 ; ALL-LE-DAG: ori [[R4:\$[0-9]+]], [[R3]], 3 108 109 ; O32-BE: fill.w [[R1:\$w[0-9]+]], [[R4]] 110 ; O32: insert.w [[R1]][1], [[R2]] 111 ; O32: splati.d $w{{.*}}, [[R1]][0] 112 113 ; MIPS64-BE: dinsu [[R4]], [[R2]], 32, 32 114 ; MIPS64-LE: dinsu [[R2]], [[R4]], 32, 32 115 ; MIPS64-BE: fill.d $w{{.*}}, [[R4]] 116 ; MIPS64-LE: fill.d $w{{.*}}, [[R2]] 117 118 ret void 119} 120 121define void @const_v4i32() nounwind { 122 ; ALL-LABEL: const_v4i32: 123 124 store volatile <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32>*@v4i32 125 ; ALL: ldi.b [[R1:\$w[0-9]+]], 0 126 127 store volatile <4 x i32> <i32 1, i32 1, i32 1, i32 1>, <4 x i32>*@v4i32 128 ; ALL: ldi.w [[R1:\$w[0-9]+]], 1 129 130 store volatile <4 x i32> <i32 1, i32 1, i32 1, i32 31>, <4 x i32>*@v4i32 131 ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ 132 ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L 133 ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L 134 ; ALL: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]]) 135 136 store volatile <4 x i32> <i32 16843009, i32 16843009, i32 16843009, i32 16843009>, <4 x i32>*@v4i32 137 ; ALL: ldi.b [[R1:\$w[0-9]+]], 1 138 139 store volatile <4 x i32> <i32 65537, i32 65537, i32 65537, i32 65537>, <4 x i32>*@v4i32 140 ; ALL: ldi.h [[R1:\$w[0-9]+]], 1 141 142 store volatile <4 x i32> <i32 1, i32 2, i32 1, i32 2>, <4 x i32>*@v4i32 143 ; -BE-DAG: ori [[R2:\$[0-9]+]], $zero, 1 144 ; O32-BE-DAG: ori [[R3:\$[0-9]+]], $zero, 1 145 ; O32-BE-DAG: ori [[R4:\$[0-9]+]], $zero, 2 146 ; O32-LE-DAG: ori [[R3:\$[0-9]+]], $zero, 2 147 ; O32-LE-DAG: ori [[R4:\$[0-9]+]], $zero, 1 148 ; O32: fill.w [[W0:\$w[0-9]+]], [[R4]] 149 ; O32: insert.w [[W0]][1], [[R3]] 150 ; O32: splati.d [[W1:\$w[0-9]+]], [[W0]] 151 152 ; MIPS64-DAG: ori [[R5:\$[0-9]+]], $zero, 2 153 ; MIPS64-DAG: ori [[R6:\$[0-9]+]], $zero, 1 154 155 ; MIPS64-BE: dinsu [[R5]], [[R6]], 32, 32 156 ; MIPS64-LE: dinsu [[R6]], [[R5]], 32, 32 157 ; MIPS64-BE: fill.d $w{{.*}}, [[R4]] 158 ; MIPS64-LE: fill.d $w{{.*}}, [[R2]] 159 160 161 store volatile <4 x i32> <i32 3, i32 4, i32 5, i32 6>, <4 x i32>*@v4i32 162 ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ 163 ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L 164 ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L 165 ; ALL: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]]) 166 167 ret void 168} 169 170define void @const_v2i64() nounwind { 171 ; ALL-LABEL: const_v2i64: 172 173 store volatile <2 x i64> <i64 0, i64 0>, <2 x i64>*@v2i64 174 ; ALL: ldi.b [[R1:\$w[0-9]+]], 0 175 176 store volatile <2 x i64> <i64 72340172838076673, i64 72340172838076673>, <2 x i64>*@v2i64 177 ; ALL: ldi.b [[R1:\$w[0-9]+]], 1 178 179 store volatile <2 x i64> <i64 281479271743489, i64 281479271743489>, <2 x i64>*@v2i64 180 ; ALL: ldi.h [[R1:\$w[0-9]+]], 1 181 182 store volatile <2 x i64> <i64 4294967297, i64 4294967297>, <2 x i64>*@v2i64 183 ; ALL: ldi.w [[R1:\$w[0-9]+]], 1 184 185 store volatile <2 x i64> <i64 1, i64 1>, <2 x i64>*@v2i64 186 ; ALL: ldi.d [[R1:\$w[0-9]+]], 1 187 188 store volatile <2 x i64> <i64 1, i64 31>, <2 x i64>*@v2i64 189 ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ 190 ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L 191 ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L 192 ; MIPS32: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]]) 193 ; MIPS64: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]]) 194 195 store volatile <2 x i64> <i64 3, i64 4>, <2 x i64>*@v2i64 196 ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ 197 ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L 198 ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L 199 ; MIPS32: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]]) 200 ; MIPS64: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]]) 201 202 ret void 203} 204 205define void @nonconst_v16i8(i8 signext %a, i8 signext %b, i8 signext %c, i8 signext %d, i8 signext %e, i8 signext %f, i8 signext %g, i8 signext %h) nounwind { 206 ; ALL-LABEL: nonconst_v16i8: 207 208 %1 = insertelement <16 x i8> undef, i8 %a, i32 0 209 %2 = insertelement <16 x i8> %1, i8 %b, i32 1 210 %3 = insertelement <16 x i8> %2, i8 %c, i32 2 211 %4 = insertelement <16 x i8> %3, i8 %d, i32 3 212 %5 = insertelement <16 x i8> %4, i8 %e, i32 4 213 %6 = insertelement <16 x i8> %5, i8 %f, i32 5 214 %7 = insertelement <16 x i8> %6, i8 %g, i32 6 215 %8 = insertelement <16 x i8> %7, i8 %h, i32 7 216 %9 = insertelement <16 x i8> %8, i8 %h, i32 8 217 %10 = insertelement <16 x i8> %9, i8 %h, i32 9 218 %11 = insertelement <16 x i8> %10, i8 %h, i32 10 219 %12 = insertelement <16 x i8> %11, i8 %h, i32 11 220 %13 = insertelement <16 x i8> %12, i8 %h, i32 12 221 %14 = insertelement <16 x i8> %13, i8 %h, i32 13 222 %15 = insertelement <16 x i8> %14, i8 %h, i32 14 223 %16 = insertelement <16 x i8> %15, i8 %h, i32 15 224 ; ALL-DAG: insert.b [[R1:\$w[0-9]+]][0], $4 225 ; ALL-DAG: insert.b [[R1]][1], $5 226 ; ALL-DAG: insert.b [[R1]][2], $6 227 ; ALL-DAG: insert.b [[R1]][3], $7 228 ; MIPS32-DAG: lw [[R2:\$[0-9]+]], 16($sp) 229 ; MIPS32-DAG: insert.b [[R1]][4], [[R2]] 230 ; MIPS64-DAG: insert.b [[R1]][4], $8 231 ; MIPS32-DAG: lw [[R3:\$[0-9]+]], 20($sp) 232 ; MIPS32-DAG: insert.b [[R1]][5], [[R3]] 233 ; MIPS64-DAG: insert.b [[R1]][5], $9 234 ; MIPS32-DAG: lw [[R4:\$[0-9]+]], 24($sp) 235 ; MIPS32-DAG: insert.b [[R1]][6], [[R4]] 236 ; MIPS64-DAG: insert.b [[R1]][6], $10 237 ; MIPS32-DAG: lw [[R5:\$[0-9]+]], 28($sp) 238 ; MIPS32-DAG: insert.b [[R1]][7], [[R5]] 239 ; MIPS64-DAG: insert.b [[R1]][7], [[R5:\$11]] 240 ; ALL-DAG: insert.b [[R1]][8], [[R5]] 241 ; ALL-DAG: insert.b [[R1]][9], [[R5]] 242 ; ALL-DAG: insert.b [[R1]][10], [[R5]] 243 ; ALL-DAG: insert.b [[R1]][11], [[R5]] 244 ; ALL-DAG: insert.b [[R1]][12], [[R5]] 245 ; ALL-DAG: insert.b [[R1]][13], [[R5]] 246 ; ALL-DAG: insert.b [[R1]][14], [[R5]] 247 ; ALL-DAG: insert.b [[R1]][15], [[R5]] 248 249 store volatile <16 x i8> %16, <16 x i8>*@v16i8 250 251 ret void 252} 253 254define void @nonconst_v8i16(i16 signext %a, i16 signext %b, i16 signext %c, i16 signext %d, i16 signext %e, i16 signext %f, i16 signext %g, i16 signext %h) nounwind { 255 ; ALL-LABEL: nonconst_v8i16: 256 257 %1 = insertelement <8 x i16> undef, i16 %a, i32 0 258 %2 = insertelement <8 x i16> %1, i16 %b, i32 1 259 %3 = insertelement <8 x i16> %2, i16 %c, i32 2 260 %4 = insertelement <8 x i16> %3, i16 %d, i32 3 261 %5 = insertelement <8 x i16> %4, i16 %e, i32 4 262 %6 = insertelement <8 x i16> %5, i16 %f, i32 5 263 %7 = insertelement <8 x i16> %6, i16 %g, i32 6 264 %8 = insertelement <8 x i16> %7, i16 %h, i32 7 265 ; ALL-DAG: insert.h [[R1:\$w[0-9]+]][0], $4 266 ; ALL-DAG: insert.h [[R1]][1], $5 267 ; ALL-DAG: insert.h [[R1]][2], $6 268 ; ALL-DAG: insert.h [[R1]][3], $7 269 ; MIPS32-DAG: lw [[R2:\$[0-9]+]], 16($sp) 270 ; MIPS32-DAG: insert.h [[R1]][4], [[R2]] 271 ; MIPS64-DAG: insert.h [[R1]][4], $8 272 ; MIPS32-DAG: lw [[R2:\$[0-9]+]], 20($sp) 273 ; MIPS32-DAG: insert.h [[R1]][5], [[R2]] 274 ; MIPS64-DAG: insert.h [[R1]][5], $9 275 ; MIPS32-DAG: lw [[R2:\$[0-9]+]], 24($sp) 276 ; MIPS32-DAG: insert.h [[R1]][6], [[R2]] 277 ; MIPS64-DAG: insert.h [[R1]][6], $10 278 ; MIPS32-DAG: lw [[R2:\$[0-9]+]], 28($sp) 279 ; MIPS32-DAG: insert.h [[R1]][7], [[R2]] 280 ; MIPS64-DAG: insert.h [[R1]][7], $11 281 282 store volatile <8 x i16> %8, <8 x i16>*@v8i16 283 284 ret void 285} 286 287define void @nonconst_v4i32(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind { 288 ; ALL-LABEL: nonconst_v4i32: 289 290 %1 = insertelement <4 x i32> undef, i32 %a, i32 0 291 %2 = insertelement <4 x i32> %1, i32 %b, i32 1 292 %3 = insertelement <4 x i32> %2, i32 %c, i32 2 293 %4 = insertelement <4 x i32> %3, i32 %d, i32 3 294 ; ALL: insert.w [[R1:\$w[0-9]+]][0], $4 295 ; ALL: insert.w [[R1]][1], $5 296 ; ALL: insert.w [[R1]][2], $6 297 ; ALL: insert.w [[R1]][3], $7 298 299 store volatile <4 x i32> %4, <4 x i32>*@v4i32 300 301 ret void 302} 303 304define void @nonconst_v2i64(i64 signext %a, i64 signext %b) nounwind { 305 ; ALL-LABEL: nonconst_v2i64: 306 307 %1 = insertelement <2 x i64> undef, i64 %a, i32 0 308 %2 = insertelement <2 x i64> %1, i64 %b, i32 1 309 ; MIPS32: insert.w [[R1:\$w[0-9]+]][0], $4 310 ; MIPS32: insert.w [[R1]][1], $5 311 ; MIPS32: insert.w [[R1]][2], $6 312 ; MIPS32: insert.w [[R1]][3], $7 313 ; MIPS64: insert.d [[R1:\$w[0-9]+]][0], $4 314 ; MIPS64: insert.d [[R1]][1], $5 315 316 store volatile <2 x i64> %2, <2 x i64>*@v2i64 317 318 ret void 319} 320 321define i32 @extract_sext_v16i8() nounwind { 322 ; ALL-LABEL: extract_sext_v16i8: 323 324 %1 = load <16 x i8>, <16 x i8>* @v16i8 325 ; ALL-DAG: ld.b [[R1:\$w[0-9]+]], 326 327 %2 = add <16 x i8> %1, %1 328 ; ALL-DAG: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]] 329 330 %3 = extractelement <16 x i8> %2, i32 1 331 %4 = sext i8 %3 to i32 332 ; ALL-DAG: copy_s.b [[R3:\$[0-9]+]], [[R1]][1] 333 ; ALL-NOT: sll 334 ; ALL-NOT: sra 335 336 ret i32 %4 337} 338 339define i32 @extract_sext_v8i16() nounwind { 340 ; ALL-LABEL: extract_sext_v8i16: 341 342 %1 = load <8 x i16>, <8 x i16>* @v8i16 343 ; ALL-DAG: ld.h [[R1:\$w[0-9]+]], 344 345 %2 = add <8 x i16> %1, %1 346 ; ALL-DAG: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1]] 347 348 %3 = extractelement <8 x i16> %2, i32 1 349 %4 = sext i16 %3 to i32 350 ; ALL-DAG: copy_s.h [[R3:\$[0-9]+]], [[R1]][1] 351 ; ALL-NOT: sll 352 ; ALL-NOT: sra 353 354 ret i32 %4 355} 356 357define i32 @extract_sext_v4i32() nounwind { 358 ; ALL-LABEL: extract_sext_v4i32: 359 360 %1 = load <4 x i32>, <4 x i32>* @v4i32 361 ; ALL-DAG: ld.w [[R1:\$w[0-9]+]], 362 363 %2 = add <4 x i32> %1, %1 364 ; ALL-DAG: addv.w [[R2:\$w[0-9]+]], [[R1]], [[R1]] 365 366 %3 = extractelement <4 x i32> %2, i32 1 367 ; ALL-DAG: copy_s.w [[R3:\$[0-9]+]], [[R1]][1] 368 369 ret i32 %3 370} 371 372define i64 @extract_sext_v2i64() nounwind { 373 ; ALL-LABEL: extract_sext_v2i64: 374 375 %1 = load <2 x i64>, <2 x i64>* @v2i64 376 ; ALL-DAG: ld.d [[R1:\$w[0-9]+]], 377 378 %2 = add <2 x i64> %1, %1 379 ; ALL-DAG: addv.d [[R2:\$w[0-9]+]], [[R1]], [[R1]] 380 381 %3 = extractelement <2 x i64> %2, i32 1 382 ; MIPS32-DAG: copy_s.w [[R3:\$[0-9]+]], [[R1]][2] 383 ; MIPS32-DAG: copy_s.w [[R4:\$[0-9]+]], [[R1]][3] 384 ; MIPS64-DAG: copy_s.d [[R3:\$[0-9]+]], [[R1]][1] 385 ; ALL-NOT: sll 386 ; ALL-NOT: sra 387 388 ret i64 %3 389} 390 391define i32 @extract_zext_v16i8() nounwind { 392 ; ALL-LABEL: extract_zext_v16i8: 393 394 %1 = load <16 x i8>, <16 x i8>* @v16i8 395 ; ALL-DAG: ld.b [[R1:\$w[0-9]+]], 396 397 %2 = add <16 x i8> %1, %1 398 ; ALL-DAG: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]] 399 400 %3 = extractelement <16 x i8> %2, i32 1 401 %4 = zext i8 %3 to i32 402 ; ALL-DAG: copy_u.b [[R3:\$[0-9]+]], [[R1]][1] 403 ; ALL-NOT: andi 404 405 ret i32 %4 406} 407 408define i32 @extract_zext_v8i16() nounwind { 409 ; ALL-LABEL: extract_zext_v8i16: 410 411 %1 = load <8 x i16>, <8 x i16>* @v8i16 412 ; ALL-DAG: ld.h [[R1:\$w[0-9]+]], 413 414 %2 = add <8 x i16> %1, %1 415 ; ALL-DAG: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1]] 416 417 %3 = extractelement <8 x i16> %2, i32 1 418 %4 = zext i16 %3 to i32 419 ; ALL-DAG: copy_u.h [[R3:\$[0-9]+]], [[R1]][1] 420 ; ALL-NOT: andi 421 422 ret i32 %4 423} 424 425define i32 @extract_zext_v4i32() nounwind { 426 ; ALL-LABEL: extract_zext_v4i32: 427 428 %1 = load <4 x i32>, <4 x i32>* @v4i32 429 ; ALL-DAG: ld.w [[R1:\$w[0-9]+]], 430 431 %2 = add <4 x i32> %1, %1 432 ; ALL-DAG: addv.w [[R2:\$w[0-9]+]], [[R1]], [[R1]] 433 434 %3 = extractelement <4 x i32> %2, i32 1 435 ; ALL-DAG: copy_{{[su]}}.w [[R3:\$[0-9]+]], [[R1]][1] 436 437 ret i32 %3 438} 439 440define i64 @extract_zext_v2i64() nounwind { 441 ; ALL-LABEL: extract_zext_v2i64: 442 443 %1 = load <2 x i64>, <2 x i64>* @v2i64 444 ; ALL-DAG: ld.d [[R1:\$w[0-9]+]], 445 446 %2 = add <2 x i64> %1, %1 447 ; ALL-DAG: addv.d [[R2:\$w[0-9]+]], [[R1]], [[R1]] 448 449 %3 = extractelement <2 x i64> %2, i32 1 450 ; MIPS32-DAG: copy_{{[su]}}.w [[R3:\$[0-9]+]], [[R1]][2] 451 ; MIPS32-DAG: copy_{{[su]}}.w [[R4:\$[0-9]+]], [[R1]][3] 452 ; MIPS64-DAG: copy_{{[su]}}.d [[R3:\$[0-9]+]], [[R1]][1] 453 ; ALL-NOT: andi 454 455 ret i64 %3 456} 457 458define i32 @extract_sext_v16i8_vidx() nounwind { 459 ; ALL-LABEL: extract_sext_v16i8_vidx: 460 461 %1 = load <16 x i8>, <16 x i8>* @v16i8 462 ; O32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v16i8)( 463 ; N32-DAG: lw [[PTR_V:\$[0-9]+]], %got_disp(v16i8)( 464 ; N64-DAG: ld [[PTR_V:\$[0-9]+]], %got_disp(v16i8)( 465 ; ALL-DAG: ld.b [[R1:\$w[0-9]+]], 0([[PTR_V]]) 466 467 %2 = add <16 x i8> %1, %1 468 ; ALL-DAG: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]] 469 470 %3 = load i32, i32* @i32 471 ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( 472 ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)( 473 ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)( 474 ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) 475 476 %4 = extractelement <16 x i8> %2, i32 %3 477 %5 = sext i8 %4 to i32 478 ; ALL-DAG: splat.b $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]] 479 ; ALL-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]] 480 ; ALL-DAG: sra [[R6:\$[0-9]+]], [[R5]], 24 481 482 ret i32 %5 483} 484 485define i32 @extract_sext_v8i16_vidx() nounwind { 486 ; ALL-LABEL: extract_sext_v8i16_vidx: 487 488 %1 = load <8 x i16>, <8 x i16>* @v8i16 489 ; O32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v8i16)( 490 ; N32-DAG: lw [[PTR_V:\$[0-9]+]], %got_disp(v8i16)( 491 ; N64-DAG: ld [[PTR_V:\$[0-9]+]], %got_disp(v8i16)( 492 ; ALL-DAG: ld.h [[R1:\$w[0-9]+]], 0([[PTR_V]]) 493 494 %2 = add <8 x i16> %1, %1 495 ; ALL-DAG: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1]] 496 497 %3 = load i32, i32* @i32 498 ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( 499 ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)( 500 ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)( 501 ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) 502 503 %4 = extractelement <8 x i16> %2, i32 %3 504 %5 = sext i16 %4 to i32 505 ; ALL-DAG: splat.h $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]] 506 ; ALL-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]] 507 ; ALL-DAG: sra [[R6:\$[0-9]+]], [[R5]], 16 508 509 ret i32 %5 510} 511 512define i32 @extract_sext_v4i32_vidx() nounwind { 513 ; ALL-LABEL: extract_sext_v4i32_vidx: 514 515 %1 = load <4 x i32>, <4 x i32>* @v4i32 516 ; O32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v4i32)( 517 ; N32-DAG: lw [[PTR_V:\$[0-9]+]], %got_disp(v4i32)( 518 ; N64-DAG: ld [[PTR_V:\$[0-9]+]], %got_disp(v4i32)( 519 ; ALL-DAG: ld.w [[R1:\$w[0-9]+]], 0([[PTR_V]]) 520 521 %2 = add <4 x i32> %1, %1 522 ; ALL-DAG: addv.w [[R2:\$w[0-9]+]], [[R1]], [[R1]] 523 524 %3 = load i32, i32* @i32 525 ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( 526 ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)( 527 ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)( 528 ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) 529 530 %4 = extractelement <4 x i32> %2, i32 %3 531 ; ALL-DAG: splat.w $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]] 532 ; ALL-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]] 533 ; ALL-NOT: sra 534 535 ret i32 %4 536} 537 538define i64 @extract_sext_v2i64_vidx() nounwind { 539 ; ALL-LABEL: extract_sext_v2i64_vidx: 540 541 %1 = load <2 x i64>, <2 x i64>* @v2i64 542 ; O32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v2i64)( 543 ; N32-DAG: lw [[PTR_V:\$[0-9]+]], %got_disp(v2i64)( 544 ; N64-DAG: ld [[PTR_V:\$[0-9]+]], %got_disp(v2i64)( 545 ; ALL-DAG: ld.d [[R1:\$w[0-9]+]], 0([[PTR_V]]) 546 547 %2 = add <2 x i64> %1, %1 548 ; ALL-DAG: addv.d [[R2:\$w[0-9]+]], [[R1]], [[R1]] 549 550 %3 = load i32, i32* @i32 551 ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( 552 ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)( 553 ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)( 554 ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) 555 ; O32-DAG: addiu [[IDY:\$[0-9]+]], [[IDX]], 1 556 557 %4 = extractelement <2 x i64> %2, i32 %3 558 ; MIPS32-DAG: splat.w $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDY]]] 559 ; MIPS32-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]] 560 ; MIPS32-DAG: splat.w $w[[R4:[0-9]+]], [[R1]]{{\[}}[[IDX]]] 561 ; MIPS32-DAG: mfc1 [[R6:\$[0-9]+]], $f[[R4]] 562 ; MIPS64-DAG: splat.d $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]] 563 ; MIPS64-DAG: dmfc1 [[R5:\$[0-9]+]], $f[[R3]] 564 ; ALL-NOT: sra 565 566 ret i64 %4 567} 568 569define i32 @extract_zext_v16i8_vidx() nounwind { 570 ; ALL-LABEL: extract_zext_v16i8_vidx: 571 572 %1 = load <16 x i8>, <16 x i8>* @v16i8 573 ; O32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v16i8)( 574 ; N32-DAG: lw [[PTR_V:\$[0-9]+]], %got_disp(v16i8)( 575 ; N64-DAG: ld [[PTR_V:\$[0-9]+]], %got_disp(v16i8)( 576 ; ALL-DAG: ld.b [[R1:\$w[0-9]+]], 0([[PTR_V]]) 577 578 %2 = add <16 x i8> %1, %1 579 ; ALL-DAG: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]] 580 581 %3 = load i32, i32* @i32 582 ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( 583 ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)( 584 ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)( 585 ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) 586 587 %4 = extractelement <16 x i8> %2, i32 %3 588 %5 = zext i8 %4 to i32 589 ; ALL-DAG: splat.b $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]] 590 ; ALL-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]] 591 ; ALL-DAG: srl [[R6:\$[0-9]+]], [[R5]], 24 592 593 ret i32 %5 594} 595 596define i32 @extract_zext_v8i16_vidx() nounwind { 597 ; ALL-LABEL: extract_zext_v8i16_vidx: 598 599 %1 = load <8 x i16>, <8 x i16>* @v8i16 600 ; O32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v8i16)( 601 ; N32-DAG: lw [[PTR_V:\$[0-9]+]], %got_disp(v8i16)( 602 ; N64-DAG: ld [[PTR_V:\$[0-9]+]], %got_disp(v8i16)( 603 ; ALL-DAG: ld.h [[R1:\$w[0-9]+]], 0([[PTR_V]]) 604 605 %2 = add <8 x i16> %1, %1 606 ; ALL-DAG: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1]] 607 608 %3 = load i32, i32* @i32 609 ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( 610 ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)( 611 ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)( 612 ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) 613 614 %4 = extractelement <8 x i16> %2, i32 %3 615 %5 = zext i16 %4 to i32 616 ; ALL-DAG: splat.h $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]] 617 ; ALL-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]] 618 ; ALL-DAG: srl [[R6:\$[0-9]+]], [[R5]], 16 619 620 ret i32 %5 621} 622 623define i32 @extract_zext_v4i32_vidx() nounwind { 624 ; ALL-LABEL: extract_zext_v4i32_vidx: 625 626 %1 = load <4 x i32>, <4 x i32>* @v4i32 627 ; O32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v4i32)( 628 ; N32-DAG: lw [[PTR_V:\$[0-9]+]], %got_disp(v4i32)( 629 ; N64-DAG: ld [[PTR_V:\$[0-9]+]], %got_disp(v4i32)( 630 ; ALL-DAG: ld.w [[R1:\$w[0-9]+]], 0([[PTR_V]]) 631 632 %2 = add <4 x i32> %1, %1 633 ; ALL-DAG: addv.w [[R2:\$w[0-9]+]], [[R1]], [[R1]] 634 635 %3 = load i32, i32* @i32 636 ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( 637 ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)( 638 ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)( 639 ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) 640 641 %4 = extractelement <4 x i32> %2, i32 %3 642 ; ALL-DAG: splat.w $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]] 643 ; ALL-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]] 644 ; ALL-NOT: srl 645 646 ret i32 %4 647} 648 649define i64 @extract_zext_v2i64_vidx() nounwind { 650 ; ALL-LABEL: extract_zext_v2i64_vidx: 651 652 %1 = load <2 x i64>, <2 x i64>* @v2i64 653 ; O32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v2i64)( 654 ; N32-DAG: lw [[PTR_V:\$[0-9]+]], %got_disp(v2i64)( 655 ; N64-DAG: ld [[PTR_V:\$[0-9]+]], %got_disp(v2i64)( 656 ; ALL-DAG: ld.d [[R1:\$w[0-9]+]], 0([[PTR_V]]) 657 658 %2 = add <2 x i64> %1, %1 659 ; ALL-DAG: addv.d [[R2:\$w[0-9]+]], [[R1]], [[R1]] 660 661 %3 = load i32, i32* @i32 662 ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( 663 ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)( 664 ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)( 665 ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) 666 ; O32-DAG: addiu [[IDY:\$[0-9]+]], [[IDX]], 1 667 668 %4 = extractelement <2 x i64> %2, i32 %3 669 ; MIPS32-DAG: splat.w $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDY]]] 670 ; MIPS32-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]] 671 ; MIPS32-DAG: splat.w $w[[R4:[0-9]+]], [[R1]]{{\[}}[[IDX]]] 672 ; MIPS32-DAG: mfc1 [[R6:\$[0-9]+]], $f[[R4]] 673 ; MIPS64-DAG: splat.d $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]] 674 ; MIPS64-DAG: dmfc1 [[R5:\$[0-9]+]], $f[[R3]] 675 ; ALL-NOT: srl 676 677 ret i64 %4 678} 679 680define void @insert_v16i8(i32 signext %a) nounwind { 681 ; ALL-LABEL: insert_v16i8: 682 683 %1 = load <16 x i8>, <16 x i8>* @v16i8 684 ; ALL-DAG: ld.b [[R1:\$w[0-9]+]], 685 686 %a2 = trunc i32 %a to i8 687 %a3 = sext i8 %a2 to i32 688 %a4 = trunc i32 %a3 to i8 689 ; ALL-NOT: andi 690 ; ALL-NOT: sra 691 692 %2 = insertelement <16 x i8> %1, i8 %a4, i32 1 693 ; ALL-DAG: insert.b [[R1]][1], $4 694 695 store <16 x i8> %2, <16 x i8>* @v16i8 696 ; ALL-DAG: st.b [[R1]] 697 698 ret void 699} 700 701define void @insert_v8i16(i32 signext %a) nounwind { 702 ; ALL-LABEL: insert_v8i16: 703 704 %1 = load <8 x i16>, <8 x i16>* @v8i16 705 ; ALL-DAG: ld.h [[R1:\$w[0-9]+]], 706 707 %a2 = trunc i32 %a to i16 708 %a3 = sext i16 %a2 to i32 709 %a4 = trunc i32 %a3 to i16 710 ; ALL-NOT: andi 711 ; ALL-NOT: sra 712 713 %2 = insertelement <8 x i16> %1, i16 %a4, i32 1 714 ; ALL-DAG: insert.h [[R1]][1], $4 715 716 store <8 x i16> %2, <8 x i16>* @v8i16 717 ; ALL-DAG: st.h [[R1]] 718 719 ret void 720} 721 722define void @insert_v4i32(i32 signext %a) nounwind { 723 ; ALL-LABEL: insert_v4i32: 724 725 %1 = load <4 x i32>, <4 x i32>* @v4i32 726 ; ALL-DAG: ld.w [[R1:\$w[0-9]+]], 727 728 ; ALL-NOT: andi 729 ; ALL-NOT: sra 730 731 %2 = insertelement <4 x i32> %1, i32 %a, i32 1 732 ; ALL-DAG: insert.w [[R1]][1], $4 733 734 store <4 x i32> %2, <4 x i32>* @v4i32 735 ; ALL-DAG: st.w [[R1]] 736 737 ret void 738} 739 740define void @insert_v2i64(i64 signext %a) nounwind { 741 ; ALL-LABEL: insert_v2i64: 742 743 %1 = load <2 x i64>, <2 x i64>* @v2i64 744 ; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]], 745 ; MIPS64-DAG: ld.d [[R1:\$w[0-9]+]], 746 747 ; ALL-NOT: andi 748 ; ALL-NOT: sra 749 750 %2 = insertelement <2 x i64> %1, i64 %a, i32 1 751 ; MIPS32-DAG: insert.w [[R1]][2], $4 752 ; MIPS32-DAG: insert.w [[R1]][3], $5 753 ; MIPS64-DAG: insert.d [[R1]][1], $4 754 755 store <2 x i64> %2, <2 x i64>* @v2i64 756 ; MIPS32-DAG: st.w [[R1]] 757 ; MIPS64-DAG: st.d [[R1]] 758 759 ret void 760} 761 762define void @insert_v16i8_vidx(i32 signext %a) nounwind { 763 ; ALL-LABEL: insert_v16i8_vidx: 764 765 %1 = load <16 x i8>, <16 x i8>* @v16i8 766 ; ALL-DAG: ld.b [[R1:\$w[0-9]+]], 767 768 %2 = load i32, i32* @i32 769 ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( 770 ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)( 771 ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)( 772 ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) 773 774 %a2 = trunc i32 %a to i8 775 %a3 = sext i8 %a2 to i32 776 %a4 = trunc i32 %a3 to i8 777 ; ALL-NOT: andi 778 ; ALL-NOT: sra 779 780 %3 = insertelement <16 x i8> %1, i8 %a4, i32 %2 781 ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[IDX]]] 782 ; ALL-DAG: insert.b [[R1]][0], $4 783 ; O32-DAG: neg [[NIDX:\$[0-9]+]], [[IDX]] 784 ; N32-DAG: neg [[NIDX:\$[0-9]+]], [[IDX]] 785 ; N64-DAG: dneg [[NIDX:\$[0-9]+]], [[IDX]] 786 ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]] 787 788 store <16 x i8> %3, <16 x i8>* @v16i8 789 ; ALL-DAG: st.b [[R1]] 790 791 ret void 792} 793 794define void @insert_v8i16_vidx(i32 signext %a) nounwind { 795 ; ALL-LABEL: insert_v8i16_vidx: 796 797 %1 = load <8 x i16>, <8 x i16>* @v8i16 798 ; ALL-DAG: ld.h [[R1:\$w[0-9]+]], 799 800 %2 = load i32, i32* @i32 801 ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( 802 ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)( 803 ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)( 804 ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) 805 806 %a2 = trunc i32 %a to i16 807 %a3 = sext i16 %a2 to i32 808 %a4 = trunc i32 %a3 to i16 809 ; ALL-NOT: andi 810 ; ALL-NOT: sra 811 812 %3 = insertelement <8 x i16> %1, i16 %a4, i32 %2 813 ; ALL-DAG: sll [[BIDX:\$[0-9]+]], [[IDX]], 1 814 ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]] 815 ; ALL-DAG: insert.h [[R1]][0], $4 816 ; O32-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]] 817 ; N32-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]] 818 ; N64-DAG: dneg [[NIDX:\$[0-9]+]], [[BIDX]] 819 ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]] 820 821 store <8 x i16> %3, <8 x i16>* @v8i16 822 ; ALL-DAG: st.h [[R1]] 823 824 ret void 825} 826 827define void @insert_v4i32_vidx(i32 signext %a) nounwind { 828 ; ALL-LABEL: insert_v4i32_vidx: 829 830 %1 = load <4 x i32>, <4 x i32>* @v4i32 831 ; ALL-DAG: ld.w [[R1:\$w[0-9]+]], 832 833 %2 = load i32, i32* @i32 834 ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( 835 ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)( 836 ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)( 837 ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) 838 839 ; ALL-NOT: andi 840 ; ALL-NOT: sra 841 842 %3 = insertelement <4 x i32> %1, i32 %a, i32 %2 843 ; ALL-DAG: sll [[BIDX:\$[0-9]+]], [[IDX]], 2 844 ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]] 845 ; ALL-DAG: insert.w [[R1]][0], $4 846 ; O32-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]] 847 ; N32-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]] 848 ; N64-DAG: dneg [[NIDX:\$[0-9]+]], [[BIDX]] 849 ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]] 850 851 store <4 x i32> %3, <4 x i32>* @v4i32 852 ; ALL-DAG: st.w [[R1]] 853 854 ret void 855} 856 857define void @insert_v2i64_vidx(i64 signext %a) nounwind { 858 ; ALL-LABEL: insert_v2i64_vidx: 859 860 %1 = load <2 x i64>, <2 x i64>* @v2i64 861 ; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]], 862 ; MIPS64-DAG: ld.d [[R1:\$w[0-9]+]], 863 864 %2 = load i32, i32* @i32 865 ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( 866 ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)( 867 ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)( 868 ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) 869 870 ; ALL-NOT: andi 871 ; ALL-NOT: sra 872 873 %3 = insertelement <2 x i64> %1, i64 %a, i32 %2 874 ; TODO: This code could be a lot better but it works. The legalizer splits 875 ; 64-bit inserts into two 32-bit inserts because there is no i64 type on 876 ; MIPS32. The obvious optimisation is to perform both insert.w's at once while 877 ; the vector is rotated. 878 ; MIPS32-DAG: sll [[BIDX:\$[0-9]+]], [[IDX]], 2 879 ; MIPS32-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]] 880 ; MIPS32-DAG: insert.w [[R1]][0], $4 881 ; MIPS32-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]] 882 ; MIPS32-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]] 883 ; MIPS32-DAG: addiu [[IDX2:\$[0-9]+]], [[IDX]], 1 884 ; MIPS32-DAG: sll [[BIDX:\$[0-9]+]], [[IDX2]], 2 885 ; MIPS32-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]] 886 ; MIPS32-DAG: insert.w [[R1]][0], $5 887 ; MIPS32-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]] 888 ; MIPS32-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]] 889 890 ; MIPS64-DAG: sll [[BIDX:\$[0-9]+]], [[IDX]], 3 891 ; MIPS64-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]] 892 ; MIPS64-DAG: insert.d [[R1]][0], $4 893 ; N32-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]] 894 ; N64-DAG: dneg [[NIDX:\$[0-9]+]], [[BIDX]] 895 ; MIPS64-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]] 896 897 store <2 x i64> %3, <2 x i64>* @v2i64 898 ; MIPS32-DAG: st.w [[R1]] 899 ; MIPS64-DAG: st.d [[R1]] 900 901 ret void 902} 903 904define void @truncstore() nounwind { 905 ; ALL-LABEL: truncstore: 906 907 store volatile <4 x i8> <i8 -1, i8 -1, i8 -1, i8 -1>, <4 x i8>*@v4i8 908 ; TODO: What code should be emitted? 909 910 ret void 911} 912