1; Test the MSA ctcmsa and cfcmsa intrinsics (which are encoded with the ELM
2; instruction format).
3
4; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -verify-machineinstrs < %s | FileCheck %s
5; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -verify-machineinstrs < %s | FileCheck %s
6
7define i32 @msa_ir_cfcmsa_test() nounwind {
8entry:
9  %0 = tail call i32 @llvm.mips.cfcmsa(i32 0)
10  ret i32 %0
11}
12
13; CHECK: msa_ir_cfcmsa_test:
14; CHECK: cfcmsa $[[R1:[0-9]+]], $0
15; CHECK: .size msa_ir_cfcmsa_test
16;
17define i32 @msa_csr_cfcmsa_test() nounwind {
18entry:
19  %0 = tail call i32 @llvm.mips.cfcmsa(i32 1)
20  ret i32 %0
21}
22
23; CHECK: msa_csr_cfcmsa_test:
24; CHECK: cfcmsa $[[R1:[0-9]+]], $1
25; CHECK: .size msa_csr_cfcmsa_test
26;
27define i32 @msa_access_cfcmsa_test() nounwind {
28entry:
29  %0 = tail call i32 @llvm.mips.cfcmsa(i32 2)
30  ret i32 %0
31}
32
33; CHECK: msa_access_cfcmsa_test:
34; CHECK: cfcmsa $[[R1:[0-9]+]], $2
35; CHECK: .size msa_access_cfcmsa_test
36;
37define i32 @msa_save_cfcmsa_test() nounwind {
38entry:
39  %0 = tail call i32 @llvm.mips.cfcmsa(i32 3)
40  ret i32 %0
41}
42
43; CHECK: msa_save_cfcmsa_test:
44; CHECK: cfcmsa $[[R1:[0-9]+]], $3
45; CHECK: .size msa_save_cfcmsa_test
46;
47define i32 @msa_modify_cfcmsa_test() nounwind {
48entry:
49  %0 = tail call i32 @llvm.mips.cfcmsa(i32 4)
50  ret i32 %0
51}
52
53; CHECK: msa_modify_cfcmsa_test:
54; CHECK: cfcmsa $[[R1:[0-9]+]], $4
55; CHECK: .size msa_modify_cfcmsa_test
56;
57define i32 @msa_request_cfcmsa_test() nounwind {
58entry:
59  %0 = tail call i32 @llvm.mips.cfcmsa(i32 5)
60  ret i32 %0
61}
62
63; CHECK: msa_request_cfcmsa_test:
64; CHECK: cfcmsa $[[R1:[0-9]+]], $5
65; CHECK: .size msa_request_cfcmsa_test
66;
67define i32 @msa_map_cfcmsa_test() nounwind {
68entry:
69  %0 = tail call i32 @llvm.mips.cfcmsa(i32 6)
70  ret i32 %0
71}
72
73; CHECK: msa_map_cfcmsa_test:
74; CHECK: cfcmsa $[[R1:[0-9]+]], $6
75; CHECK: .size msa_map_cfcmsa_test
76;
77define i32 @msa_unmap_cfcmsa_test() nounwind {
78entry:
79  %0 = tail call i32 @llvm.mips.cfcmsa(i32 7)
80  ret i32 %0
81}
82
83; CHECK: msa_unmap_cfcmsa_test:
84; CHECK: cfcmsa $[[R1:[0-9]+]], $7
85; CHECK: .size msa_unmap_cfcmsa_test
86;
87define i32 @msa_invalid_reg_cfcmsa_test() nounwind {
88entry:
89  %0 = tail call i32 @llvm.mips.cfcmsa(i32 8)
90  ret i32 %0
91}
92
93; CHECK-LABEL: msa_invalid_reg_cfcmsa_test:
94; CHECK: cfcmsa ${{[0-9]+}}, $8
95;
96define void @msa_ir_ctcmsa_test() nounwind {
97entry:
98  tail call void @llvm.mips.ctcmsa(i32 0, i32 1)
99  ret void
100}
101
102; CHECK: msa_ir_ctcmsa_test:
103; CHECK: ctcmsa $0
104; CHECK: .size msa_ir_ctcmsa_test
105;
106define void @msa_csr_ctcmsa_test() nounwind {
107entry:
108  tail call void @llvm.mips.ctcmsa(i32 1, i32 1)
109  ret void
110}
111
112; CHECK: msa_csr_ctcmsa_test:
113; CHECK: ctcmsa $1
114; CHECK: .size msa_csr_ctcmsa_test
115;
116define void @msa_access_ctcmsa_test() nounwind {
117entry:
118  tail call void @llvm.mips.ctcmsa(i32 2, i32 1)
119  ret void
120}
121
122; CHECK: msa_access_ctcmsa_test:
123; CHECK: ctcmsa $2
124; CHECK: .size msa_access_ctcmsa_test
125;
126define void @msa_save_ctcmsa_test() nounwind {
127entry:
128  tail call void @llvm.mips.ctcmsa(i32 3, i32 1)
129  ret void
130}
131
132; CHECK: msa_save_ctcmsa_test:
133; CHECK: ctcmsa $3
134; CHECK: .size msa_save_ctcmsa_test
135;
136define void @msa_modify_ctcmsa_test() nounwind {
137entry:
138  tail call void @llvm.mips.ctcmsa(i32 4, i32 1)
139  ret void
140}
141
142; CHECK: msa_modify_ctcmsa_test:
143; CHECK: ctcmsa $4
144; CHECK: .size msa_modify_ctcmsa_test
145;
146define void @msa_request_ctcmsa_test() nounwind {
147entry:
148  tail call void @llvm.mips.ctcmsa(i32 5, i32 1)
149  ret void
150}
151
152; CHECK: msa_request_ctcmsa_test:
153; CHECK: ctcmsa $5
154; CHECK: .size msa_request_ctcmsa_test
155;
156define void @msa_map_ctcmsa_test() nounwind {
157entry:
158  tail call void @llvm.mips.ctcmsa(i32 6, i32 1)
159  ret void
160}
161
162; CHECK: msa_map_ctcmsa_test:
163; CHECK: ctcmsa $6
164; CHECK: .size msa_map_ctcmsa_test
165;
166define void @msa_unmap_ctcmsa_test() nounwind {
167entry:
168  tail call void @llvm.mips.ctcmsa(i32 7, i32 1)
169  ret void
170}
171
172; CHECK: msa_unmap_ctcmsa_test:
173; CHECK: ctcmsa $7
174; CHECK: .size msa_unmap_ctcmsa_test
175;
176define void @msa_invalid_reg_ctcmsa_test() nounwind {
177entry:
178  tail call void @llvm.mips.ctcmsa(i32 8, i32 1)
179  ret void
180}
181
182; CHECK: msa_invalid_reg_ctcmsa_test:
183; CHECK: ctcmsa $8
184;
185declare i32 @llvm.mips.cfcmsa(i32) nounwind
186declare void @llvm.mips.ctcmsa(i32, i32) nounwind
187