1; Test the MSA intrinsics that are encoded with the I5 instruction format and 2; are loads or stores. 3 4; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s 5; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s 6 7@llvm_mips_ld_b_ARG = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 8@llvm_mips_ld_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 9 10define void @llvm_mips_ld_b_test() nounwind { 11entry: 12 %0 = bitcast <16 x i8>* @llvm_mips_ld_b_ARG to i8* 13 %1 = tail call <16 x i8> @llvm.mips.ld.b(i8* %0, i32 16) 14 store <16 x i8> %1, <16 x i8>* @llvm_mips_ld_b_RES 15 ret void 16} 17 18declare <16 x i8> @llvm.mips.ld.b(i8*, i32) nounwind 19 20; CHECK: llvm_mips_ld_b_test: 21; CHECK: ld.b [[R1:\$w[0-9]+]], 16( 22; CHECK: st.b 23; CHECK: .size llvm_mips_ld_b_test 24; 25 26define void @llvm_mips_ld_b_unaligned_test() nounwind { 27entry: 28 %0 = bitcast <16 x i8>* @llvm_mips_ld_b_ARG to i8* 29 %1 = tail call <16 x i8> @llvm.mips.ld.b(i8* %0, i32 9) 30 store <16 x i8> %1, <16 x i8>* @llvm_mips_ld_b_RES 31 ret void 32} 33 34; CHECK: llvm_mips_ld_b_unaligned_test: 35; CHECK: ld.b [[R1:\$w[0-9]+]], 9( 36; CHECK: st.b 37; CHECK: .size llvm_mips_ld_b_unaligned_test 38; 39 40define void @llvm_mips_ld_b_valid_range_tests() nounwind { 41entry: 42 %0 = bitcast <16 x i8>* @llvm_mips_ld_b_ARG to i8* 43 %1 = tail call <16 x i8> @llvm.mips.ld.b(i8* %0, i32 -512) 44 store <16 x i8> %1, <16 x i8>* @llvm_mips_ld_b_RES 45 %2 = tail call <16 x i8> @llvm.mips.ld.b(i8* %0, i32 511) 46 store <16 x i8> %2, <16 x i8>* @llvm_mips_ld_b_RES 47 ret void 48} 49 50; CHECK: llvm_mips_ld_b_valid_range_tests: 51; CHECK: ld.b [[R1:\$w[0-9]+]], -512( 52; CHECK: st.b 53; CHECK: ld.b [[R1:\$w[0-9]+]], 511( 54; CHECK: st.b 55; CHECK: .size llvm_mips_ld_b_valid_range_tests 56; 57 58define void @llvm_mips_ld_b_invalid_range_tests() nounwind { 59entry: 60 %0 = bitcast <16 x i8>* @llvm_mips_ld_b_ARG to i8* 61 %1 = tail call <16 x i8> @llvm.mips.ld.b(i8* %0, i32 -513) 62 store <16 x i8> %1, <16 x i8>* @llvm_mips_ld_b_RES 63 %2 = tail call <16 x i8> @llvm.mips.ld.b(i8* %0, i32 512) 64 store <16 x i8> %2, <16 x i8>* @llvm_mips_ld_b_RES 65 ret void 66} 67 68; CHECK: llvm_mips_ld_b_invalid_range_tests: 69; CHECK: addiu $3, $2, -513 70; CHECK: ld.b [[R1:\$w[0-9]+]], 0( 71; CHECK: st.b 72; CHECK: addiu $2, $2, 512 73; CHECK: ld.b [[R1:\$w[0-9]+]], 0( 74; CHECK: st.b 75; CHECK: .size llvm_mips_ld_b_invalid_range_tests 76; 77 78@llvm_mips_ld_h_ARG = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 79@llvm_mips_ld_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 80 81define void @llvm_mips_ld_h_test() nounwind { 82entry: 83 %0 = bitcast <8 x i16>* @llvm_mips_ld_h_ARG to i8* 84 %1 = tail call <8 x i16> @llvm.mips.ld.h(i8* %0, i32 16) 85 store <8 x i16> %1, <8 x i16>* @llvm_mips_ld_h_RES 86 ret void 87} 88 89declare <8 x i16> @llvm.mips.ld.h(i8*, i32) nounwind 90 91; CHECK: llvm_mips_ld_h_test: 92; CHECK: ld.h [[R1:\$w[0-9]+]], 16( 93; CHECK: st.h 94; CHECK: .size llvm_mips_ld_h_test 95; 96 97define void @llvm_mips_ld_h_unaligned_test() nounwind { 98entry: 99 %0 = bitcast <8 x i16>* @llvm_mips_ld_h_ARG to i8* 100 %1 = tail call <8 x i16> @llvm.mips.ld.h(i8* %0, i32 9) 101 store <8 x i16> %1, <8 x i16>* @llvm_mips_ld_h_RES 102 ret void 103} 104 105; CHECK: llvm_mips_ld_h_unaligned_test: 106; CHECK: addiu $2, $2, 9 107; CHECK: ld.h [[R1:\$w[0-9]+]], 0($2) 108; CHECK: st.h 109; CHECK: .size llvm_mips_ld_h_unaligned_test 110; 111 112define void @llvm_mips_ld_h_valid_range_tests() nounwind { 113entry: 114 %0 = bitcast <8 x i16>* @llvm_mips_ld_h_ARG to i8* 115 %1 = tail call <8 x i16> @llvm.mips.ld.h(i8* %0, i32 -1024) 116 store <8 x i16> %1, <8 x i16>* @llvm_mips_ld_h_RES 117 %2 = tail call <8 x i16> @llvm.mips.ld.h(i8* %0, i32 1022) 118 store <8 x i16> %2, <8 x i16>* @llvm_mips_ld_h_RES 119 ret void 120} 121 122; CHECK: llvm_mips_ld_h_valid_range_tests: 123; CHECK: ld.h [[R1:\$w[0-9]+]], -1024( 124; CHECK: st.h 125; CHECK: ld.h [[R1:\$w[0-9]+]], 1022( 126; CHECK: st.h 127; CHECK: .size llvm_mips_ld_h_valid_range_tests 128; 129 130define void @llvm_mips_ld_h_invalid_range_tests() nounwind { 131entry: 132 %0 = bitcast <8 x i16>* @llvm_mips_ld_h_ARG to i8* 133 %1 = tail call <8 x i16> @llvm.mips.ld.h(i8* %0, i32 -1026) 134 store <8 x i16> %1, <8 x i16>* @llvm_mips_ld_h_RES 135 %2 = tail call <8 x i16> @llvm.mips.ld.h(i8* %0, i32 1024) 136 store <8 x i16> %2, <8 x i16>* @llvm_mips_ld_h_RES 137 ret void 138} 139 140; CHECK: llvm_mips_ld_h_invalid_range_tests: 141; CHECK: addiu $3, $2, -1026 142; CHECK: ld.h [[R1:\$w[0-9]+]], 0( 143; CHECK: st.h 144; CHECK: addiu $2, $2, 1024 145; CHECK: ld.h [[R1:\$w[0-9]+]], 0( 146; CHECK: st.h 147; CHECK: .size llvm_mips_ld_h_invalid_range_tests 148; 149 150@llvm_mips_ld_w_ARG = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 151@llvm_mips_ld_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 152 153define void @llvm_mips_ld_w_test() nounwind { 154entry: 155 %0 = bitcast <4 x i32>* @llvm_mips_ld_w_ARG to i8* 156 %1 = tail call <4 x i32> @llvm.mips.ld.w(i8* %0, i32 16) 157 store <4 x i32> %1, <4 x i32>* @llvm_mips_ld_w_RES 158 ret void 159} 160 161declare <4 x i32> @llvm.mips.ld.w(i8*, i32) nounwind 162 163; CHECK: llvm_mips_ld_w_test: 164; CHECK: ld.w [[R1:\$w[0-9]+]], 16( 165; CHECK: st.w 166; CHECK: .size llvm_mips_ld_w_test 167; 168@llvm_mips_ld_d_ARG = global <2 x i64> <i64 0, i64 1>, align 16 169@llvm_mips_ld_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 170 171define void @llvm_mips_ld_w_unaligned_test() nounwind { 172entry: 173 %0 = bitcast <4 x i32>* @llvm_mips_ld_w_ARG to i8* 174 %1 = tail call <4 x i32> @llvm.mips.ld.w(i8* %0, i32 9) 175 store <4 x i32> %1, <4 x i32>* @llvm_mips_ld_w_RES 176 ret void 177} 178 179; CHECK: llvm_mips_ld_w_unaligned_test: 180; CHECK: addiu $2, $2, 9 181; CHECK: ld.w [[R1:\$w[0-9]+]], 0($2) 182; CHECK: st.w 183; CHECK: .size llvm_mips_ld_w_unaligned_test 184; 185 186define void @llvm_mips_ld_w_valid_range_tests() nounwind { 187entry: 188 %0 = bitcast <4 x i32>* @llvm_mips_ld_w_ARG to i8* 189 %1 = tail call <4 x i32> @llvm.mips.ld.w(i8* %0, i32 -2048) 190 store <4 x i32> %1, <4 x i32>* @llvm_mips_ld_w_RES 191 %2 = tail call <4 x i32> @llvm.mips.ld.w(i8* %0, i32 2044) 192 store <4 x i32> %2, <4 x i32>* @llvm_mips_ld_w_RES 193 ret void 194} 195 196; CHECK: llvm_mips_ld_w_valid_range_tests: 197; CHECK: ld.w [[R1:\$w[0-9]+]], -2048( 198; CHECK: st.w 199; CHECK: ld.w [[R1:\$w[0-9]+]], 2044( 200; CHECK: st.w 201; CHECK: .size llvm_mips_ld_w_valid_range_tests 202; 203 204define void @llvm_mips_ld_w_invalid_range_tests() nounwind { 205entry: 206 %0 = bitcast <4 x i32>* @llvm_mips_ld_w_ARG to i8* 207 %1 = tail call <4 x i32> @llvm.mips.ld.w(i8* %0, i32 -2052) 208 store <4 x i32> %1, <4 x i32>* @llvm_mips_ld_w_RES 209 %2 = tail call <4 x i32> @llvm.mips.ld.w(i8* %0, i32 2048) 210 store <4 x i32> %2, <4 x i32>* @llvm_mips_ld_w_RES 211 ret void 212} 213 214; CHECK: llvm_mips_ld_w_invalid_range_tests: 215; CHECK: addiu $3, $2, -2052 216; CHECK: ld.w [[R1:\$w[0-9]+]], 0( 217; CHECK: st.w 218; CHECK: addiu $2, $2, 2048 219; CHECK: ld.w [[R1:\$w[0-9]+]], 0( 220; CHECK: st.w 221; CHECK: .size llvm_mips_ld_w_invalid_range_tests 222; 223 224define void @llvm_mips_ld_d_test() nounwind { 225entry: 226 %0 = bitcast <2 x i64>* @llvm_mips_ld_d_ARG to i8* 227 %1 = tail call <2 x i64> @llvm.mips.ld.d(i8* %0, i32 16) 228 store <2 x i64> %1, <2 x i64>* @llvm_mips_ld_d_RES 229 ret void 230} 231 232declare <2 x i64> @llvm.mips.ld.d(i8*, i32) nounwind 233 234; CHECK: llvm_mips_ld_d_test: 235; CHECK: ld.d [[R1:\$w[0-9]+]], 16( 236; CHECK: st.d 237; CHECK: .size llvm_mips_ld_d_test 238; 239 240define void @llvm_mips_ld_d_unaligned_test() nounwind { 241entry: 242 %0 = bitcast <2 x i64>* @llvm_mips_ld_d_ARG to i8* 243 %1 = tail call <2 x i64> @llvm.mips.ld.d(i8* %0, i32 9) 244 store <2 x i64> %1, <2 x i64>* @llvm_mips_ld_d_RES 245 ret void 246} 247 248; CHECK: llvm_mips_ld_d_unaligned_test: 249; CHECK: addiu $2, $2, 9 250; CHECK: ld.d [[R1:\$w[0-9]+]], 0($2) 251; CHECK: st.d 252; CHECK: .size llvm_mips_ld_d_unaligned_test 253; 254 255define void @llvm_mips_ld_d_valid_range_tests() nounwind { 256entry: 257 %0 = bitcast <2 x i64>* @llvm_mips_ld_d_ARG to i8* 258 %1 = tail call <2 x i64> @llvm.mips.ld.d(i8* %0, i32 -4096) 259 store <2 x i64> %1, <2 x i64>* @llvm_mips_ld_d_RES 260 %2 = tail call <2 x i64> @llvm.mips.ld.d(i8* %0, i32 4088) 261 store <2 x i64> %2, <2 x i64>* @llvm_mips_ld_d_RES 262 ret void 263} 264 265; CHECK: llvm_mips_ld_d_valid_range_tests: 266; CHECK: ld.d [[R1:\$w[0-9]+]], -4096( 267; CHECK: st.d 268; CHECK: ld.d [[R1:\$w[0-9]+]], 4088( 269; CHECK: st.d 270; CHECK: .size llvm_mips_ld_d_valid_range_tests 271; 272 273define void @llvm_mips_ld_d_invalid_range_tests() nounwind { 274entry: 275 %0 = bitcast <2 x i64>* @llvm_mips_ld_d_ARG to i8* 276 %1 = tail call <2 x i64> @llvm.mips.ld.d(i8* %0, i32 -4104) 277 store <2 x i64> %1, <2 x i64>* @llvm_mips_ld_d_RES 278 %2 = tail call <2 x i64> @llvm.mips.ld.d(i8* %0, i32 4096) 279 store <2 x i64> %2, <2 x i64>* @llvm_mips_ld_d_RES 280 ret void 281} 282 283; CHECK: llvm_mips_ld_d_invalid_range_tests: 284; CHECK: addiu $3, $2, -4104 285; CHECK: ld.d [[R1:\$w[0-9]+]], 0( 286; CHECK: st.d 287; CHECK: addiu $2, $2, 4096 288; CHECK: ld.d [[R1:\$w[0-9]+]], 0( 289; CHECK: st.d 290; CHECK: .size llvm_mips_ld_d_invalid_range_tests 291; 292 293 294 295@llvm_mips_st_b_ARG = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 296@llvm_mips_st_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 297 298define void @llvm_mips_st_b_test() nounwind { 299entry: 300 %0 = load <16 x i8>, <16 x i8>* @llvm_mips_st_b_ARG 301 %1 = bitcast <16 x i8>* @llvm_mips_st_b_RES to i8* 302 tail call void @llvm.mips.st.b(<16 x i8> %0, i8* %1, i32 16) 303 ret void 304} 305 306declare void @llvm.mips.st.b(<16 x i8>, i8*, i32) nounwind 307 308; CHECK: llvm_mips_st_b_test: 309; CHECK: ld.b 310; CHECK: st.b [[R1:\$w[0-9]+]], 16( 311; CHECK: .size llvm_mips_st_b_test 312; 313 314define void @llvm_mips_st_b_unaligned_test() nounwind { 315entry: 316 %0 = load <16 x i8>, <16 x i8>* @llvm_mips_st_b_ARG 317 %1 = bitcast <16 x i8>* @llvm_mips_st_b_RES to i8* 318 tail call void @llvm.mips.st.b(<16 x i8> %0, i8* %1, i32 9) 319 ret void 320} 321 322; CHECK: llvm_mips_st_b_unaligned_test: 323; CHECK: ld.b 324; CHECK: st.b [[R1:\$w[0-9]+]], 9( 325; CHECK: .size llvm_mips_st_b_unaligned_test 326; 327 328define void @llvm_mips_st_b_valid_range_tests() nounwind { 329entry: 330 %0 = load <16 x i8>, <16 x i8>* @llvm_mips_st_b_ARG 331 %1 = bitcast <16 x i8>* @llvm_mips_st_b_RES to i8* 332 tail call void @llvm.mips.st.b(<16 x i8> %0, i8* %1, i32 -512) 333 tail call void @llvm.mips.st.b(<16 x i8> %0, i8* %1, i32 511) 334 ret void 335} 336 337; CHECK: llvm_mips_st_b_valid_range_tests: 338; CHECK: ld.b 339; CHECK-DAG: st.b [[R1:\$w[0-9]+]], -512( 340; CHECK-DAG: st.b [[R1:\$w[0-9]+]], 511( 341; CHECK: .size llvm_mips_st_b_valid_range_tests 342; 343 344define void @llvm_mips_st_b_invalid_range_tests() nounwind { 345entry: 346 %0 = load <16 x i8>, <16 x i8>* @llvm_mips_st_b_ARG 347 %1 = bitcast <16 x i8>* @llvm_mips_st_b_RES to i8* 348 tail call void @llvm.mips.st.b(<16 x i8> %0, i8* %1, i32 -513) 349 tail call void @llvm.mips.st.b(<16 x i8> %0, i8* %1, i32 512) 350 ret void 351} 352 353; CHECK: llvm_mips_st_b_invalid_range_tests: 354; CHECK: addiu $2, $1, 512 355; CHECK: ld.b 356; CHECK: st.b [[R1:\$w[0-9]+]], 0( 357; CHECK: addiu $1, $1, -513 358; CHECK: st.b [[R1:\$w[0-9]+]], 0( 359; CHECK: .size llvm_mips_st_b_invalid_range_tests 360; 361 362@llvm_mips_st_h_ARG = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 363@llvm_mips_st_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 364 365define void @llvm_mips_st_h_test() nounwind { 366entry: 367 %0 = load <8 x i16>, <8 x i16>* @llvm_mips_st_h_ARG 368 %1 = bitcast <8 x i16>* @llvm_mips_st_h_RES to i8* 369 tail call void @llvm.mips.st.h(<8 x i16> %0, i8* %1, i32 16) 370 ret void 371} 372 373declare void @llvm.mips.st.h(<8 x i16>, i8*, i32) nounwind 374 375; CHECK: llvm_mips_st_h_test: 376; CHECK: ld.h 377; CHECK: st.h [[R1:\$w[0-9]+]], 16( 378; CHECK: .size llvm_mips_st_h_test 379; 380 381define void @llvm_mips_st_h_unaligned_test() nounwind { 382entry: 383 %0 = load <8 x i16>, <8 x i16>* @llvm_mips_st_h_ARG 384 %1 = bitcast <8 x i16>* @llvm_mips_st_h_RES to i8* 385 tail call void @llvm.mips.st.h(<8 x i16> %0, i8* %1, i32 9) 386 ret void 387} 388 389; CHECK: llvm_mips_st_h_unaligned_test: 390; CHECK: addiu $1, $1, 9 391; CHECK: ld.h 392; CHECK: st.h [[R1:\$w[0-9]+]], 0($1) 393; CHECK: .size llvm_mips_st_h_unaligned_test 394; 395 396define void @llvm_mips_st_h_valid_range_tests() nounwind { 397entry: 398 %0 = load <8 x i16>, <8 x i16>* @llvm_mips_st_h_ARG 399 %1 = bitcast <8 x i16>* @llvm_mips_st_h_RES to i8* 400 tail call void @llvm.mips.st.h(<8 x i16> %0, i8* %1, i32 -1024) 401 tail call void @llvm.mips.st.h(<8 x i16> %0, i8* %1, i32 1022) 402 ret void 403} 404 405; CHECK: llvm_mips_st_h_valid_range_tests: 406; CHECK: ld.h 407; CHECK-DAG: st.h [[R1:\$w[0-9]+]], -1024( 408; CHECK-DAG: st.h [[R1:\$w[0-9]+]], 1022( 409; CHECK: .size llvm_mips_st_h_valid_range_tests 410; 411 412define void @llvm_mips_st_h_invalid_range_tests() nounwind { 413entry: 414 %0 = load <8 x i16>, <8 x i16>* @llvm_mips_st_h_ARG 415 %1 = bitcast <8 x i16>* @llvm_mips_st_h_RES to i8* 416 tail call void @llvm.mips.st.h(<8 x i16> %0, i8* %1, i32 -1026) 417 tail call void @llvm.mips.st.h(<8 x i16> %0, i8* %1, i32 1024) 418 ret void 419} 420 421; CHECK: llvm_mips_st_h_invalid_range_tests: 422; CHECK: addiu $2, $1, 1024 423; CHECK: ld.h 424; CHECK: st.h [[R1:\$w[0-9]+]], 0( 425; CHECK: addiu $1, $1, -1026 426; CHECK: st.h [[R1:\$w[0-9]+]], 0( 427; CHECK: .size llvm_mips_st_h_invalid_range_tests 428; 429 430@llvm_mips_st_w_ARG = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 431@llvm_mips_st_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 432 433define void @llvm_mips_st_w_test() nounwind { 434entry: 435 %0 = load <4 x i32>, <4 x i32>* @llvm_mips_st_w_ARG 436 %1 = bitcast <4 x i32>* @llvm_mips_st_w_RES to i8* 437 tail call void @llvm.mips.st.w(<4 x i32> %0, i8* %1, i32 16) 438 ret void 439} 440 441declare void @llvm.mips.st.w(<4 x i32>, i8*, i32) nounwind 442 443; CHECK: llvm_mips_st_w_test: 444; CHECK: ld.w 445; CHECK: st.w [[R1:\$w[0-9]+]], 16( 446; CHECK: .size llvm_mips_st_w_test 447; 448 449define void @llvm_mips_st_w_unaligned_test() nounwind { 450entry: 451 %0 = load <4 x i32>, <4 x i32>* @llvm_mips_st_w_ARG 452 %1 = bitcast <4 x i32>* @llvm_mips_st_w_RES to i8* 453 tail call void @llvm.mips.st.w(<4 x i32> %0, i8* %1, i32 9) 454 ret void 455} 456 457; CHECK: llvm_mips_st_w_unaligned_test: 458; CHECK: addiu $1, $1, 9 459; CHECK: ld.w 460; CHECK: st.w [[R1:\$w[0-9]+]], 0($1) 461; CHECK: .size llvm_mips_st_w_unaligned_test 462; 463 464define void @llvm_mips_st_w_valid_range_tests() nounwind { 465entry: 466 %0 = load <4 x i32>, <4 x i32>* @llvm_mips_st_w_ARG 467 %1 = bitcast <4 x i32>* @llvm_mips_st_w_RES to i8* 468 tail call void @llvm.mips.st.w(<4 x i32> %0, i8* %1, i32 -2048) 469 tail call void @llvm.mips.st.w(<4 x i32> %0, i8* %1, i32 2044) 470 ret void 471} 472 473; CHECK: llvm_mips_st_w_valid_range_tests: 474; CHECK: ld.w 475; CHECK-DAG: st.w [[R1:\$w[0-9]+]], -2048( 476; CHECK-DAG: st.w [[R1:\$w[0-9]+]], 2044( 477; CHECK: .size llvm_mips_st_w_valid_range_tests 478; 479 480define void @llvm_mips_st_w_invalid_range_tests() nounwind { 481entry: 482 %0 = load <4 x i32>, <4 x i32>* @llvm_mips_st_w_ARG 483 %1 = bitcast <4 x i32>* @llvm_mips_st_w_RES to i8* 484 tail call void @llvm.mips.st.w(<4 x i32> %0, i8* %1, i32 -2052) 485 tail call void @llvm.mips.st.w(<4 x i32> %0, i8* %1, i32 2048) 486 ret void 487} 488 489; CHECK: llvm_mips_st_w_invalid_range_tests: 490; CHECK: addiu $2, $1, 2048 491; CHECK: ld.w 492; CHECK: st.w [[R1:\$w[0-9]+]], 0( 493; CHECK: addiu $1, $1, -2052 494; CHECK: st.w [[R1:\$w[0-9]+]], 0( 495; CHECK: .size llvm_mips_st_w_invalid_range_tests 496; 497 498@llvm_mips_st_d_ARG = global <2 x i64> <i64 0, i64 1>, align 16 499@llvm_mips_st_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 500 501define void @llvm_mips_st_d_test() nounwind { 502entry: 503 %0 = load <2 x i64>, <2 x i64>* @llvm_mips_st_d_ARG 504 %1 = bitcast <2 x i64>* @llvm_mips_st_d_RES to i8* 505 tail call void @llvm.mips.st.d(<2 x i64> %0, i8* %1, i32 16) 506 ret void 507} 508 509declare void @llvm.mips.st.d(<2 x i64>, i8*, i32) nounwind 510 511; CHECK: llvm_mips_st_d_test: 512; CHECK: ld.d 513; CHECK: st.d [[R1:\$w[0-9]+]], 16( 514; CHECK: .size llvm_mips_st_d_test 515; 516 517define void @llvm_mips_st_d_unaligned_test() nounwind { 518entry: 519 %0 = load <2 x i64>, <2 x i64>* @llvm_mips_st_d_ARG 520 %1 = bitcast <2 x i64>* @llvm_mips_st_d_RES to i8* 521 tail call void @llvm.mips.st.d(<2 x i64> %0, i8* %1, i32 9) 522 ret void 523} 524 525; CHECK: llvm_mips_st_d_unaligned_test: 526; CHECK: addiu $1, $1, 9 527; CHECK: ld.d 528; CHECK: st.d [[R1:\$w[0-9]+]], 0($1) 529; CHECK: .size llvm_mips_st_d_unaligned_test 530; 531 532define void @llvm_mips_st_d_valid_range_tests() nounwind { 533entry: 534 %0 = load <2 x i64>, <2 x i64>* @llvm_mips_st_d_ARG 535 %1 = bitcast <2 x i64>* @llvm_mips_st_d_RES to i8* 536 tail call void @llvm.mips.st.d(<2 x i64> %0, i8* %1, i32 -4096) 537 tail call void @llvm.mips.st.d(<2 x i64> %0, i8* %1, i32 4088) 538 ret void 539} 540 541; CHECK: llvm_mips_st_d_valid_range_tests: 542; CHECK: ld.d 543; CHECK-DAG: st.d [[R1:\$w[0-9]+]], -4096( 544; CHECK-DAG: st.d [[R1:\$w[0-9]+]], 4088( 545; CHECK: .size llvm_mips_st_d_valid_range_tests 546; 547 548define void @llvm_mips_st_d_invalid_range_tests() nounwind { 549entry: 550 %0 = load <2 x i64>, <2 x i64>* @llvm_mips_st_d_ARG 551 %1 = bitcast <2 x i64>* @llvm_mips_st_d_RES to i8* 552 tail call void @llvm.mips.st.d(<2 x i64> %0, i8* %1, i32 -4104) 553 tail call void @llvm.mips.st.d(<2 x i64> %0, i8* %1, i32 4096) 554 ret void 555} 556 557; CHECK: llvm_mips_st_d_invalid_range_tests: 558; CHECK: addiu $2, $1, 4096 559; CHECK: ld.d 560; CHECK: st.d [[R1:\$w[0-9]+]], 0( 561; CHECK: addiu $1, $1, -4104 562; CHECK: st.d [[R1:\$w[0-9]+]], 0( 563; CHECK: .size llvm_mips_st_d_invalid_range_tests 564; 565