1; RUN: llc -march=mipsel -mcpu=mips32 < %s \
2; RUN:   | FileCheck %s -check-prefixes=ALL,ODDSPREG,ODDSPREG-NO-EMIT
3; RUN: llc -march=mipsel -mcpu=mips32 -mattr=+nooddspreg < %s \
4; RUN:   | FileCheck %s -check-prefixes=ALL,NOODDSPREG
5; RUN: llc -march=mipsel -mcpu=mips32r6 -mattr=fp64 < %s \
6; RUN:   | FileCheck %s -check-prefixes=ALL,ODDSPREG,ODDSPREG-NO-EMIT
7; RUN: llc -march=mipsel -mcpu=mips32r6 -mattr=fp64,+nooddspreg < %s \
8; RUN:   | FileCheck %s -check-prefixes=ALL,NOODDSPREG
9; RUN: llc -march=mipsel -mcpu=mips32r6 -mattr=fpxx,-nooddspreg < %s \
10; RUN:   | FileCheck %s -check-prefixes=ALL,ODDSPREG,ODDSPREG-EMIT
11
12; We don't emit a directive unless we need to. This is to support versions of
13; GAS which do not support the directive.
14; ODDSPREG-EMIT:        .module oddspreg
15; ODDSPREG-NO-EMIT-NOT: .module oddspreg
16; NOODDSPREG:           .module nooddspreg
17
18define float @two_floats(float %a) {
19entry:
20  ; Clobber all except $f12 and $f13
21  ;
22  ; The intention is that if odd single precision registers are permitted, the
23  ; allocator will choose $f12 and $f13 to avoid the spill/reload.
24  ;
25  ; On the other hand, if odd single precision registers are not permitted, it
26  ; will be forced to spill/reload either %a or %0.
27  ;
28  ; This is affected by scheduling as the new machine scheduler schedules the
29  ; two adds together, avoiding the spill+reload.
30
31  %0 = fadd float %a, 1.0
32  call void asm "# Clobber", "~{$f0},~{$f1},~{$f2},~{$f3},~{$f4},~{$f5},~{$f6},~{$f7},~{$f8},~{$f9},~{$f10},~{$f11},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"()
33  %1 = fadd float %a, %0
34  ret float %1
35}
36
37; ALL-LABEL:  two_floats:
38; ODDSPREG:       add.s $f[[RES:[0-9]]], $f12, ${{f[0-9]+}}
39; ODDSPREG:       add.s ${{f[0-9]+}}, $f12, $f[[RES]]
40; ODDSPREG-NOT:   swc1
41; ODDSPREG-NOT:   lwc1
42
43; NOODDSPREG:     add.s $[[T0:f[0-9]*[02468]]], $f12, ${{f[0-9]+}}
44; NOODDSPREG-NOT: swc1 $[[T0]],
45; NOODDSPREG-NOT: lwc1 $[[T1:f[0-9]*[02468]]],
46; NOODDSPREG:     add.s ${{f[0-9]+}}, $f12, $[[T0]]
47
48define double @two_doubles(double %a) {
49entry:
50  ; Clobber all except $f12 and $f13
51  ;
52  ; -mno-odd-sp-reg doesn't need to affect double precision values so both cases
53  ; use $f12 and $f13.
54
55  %0 = fadd double %a, 1.0
56  call void asm "# Clobber", "~{$f0},~{$f1},~{$f2},~{$f3},~{$f4},~{$f5},~{$f6},~{$f7},~{$f8},~{$f9},~{$f10},~{$f11},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"()
57  %1 = fadd double %a, %0
58  ret double %1
59}
60
61; ALL-LABEL: two_doubles:
62; ALL-DAG:        add.d $[[T0:f[0-9]+]], $f12, ${{f[0-9]+}}
63; ALL-DAG:        add.d ${{f[0-9]+}}, $f12, $[[T0]]
64
65
66; INVALID: -mattr=+nooddspreg is not currently permitted for a 32-bit FPU register file (FR=0 mode).
67