1; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \
2; RUN: -code-model=small < %s | FileCheck %s --check-prefix=SMALL
3
4; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \
5; RUN: -code-model=large < %s | FileCheck %s --check-prefix=LARGE
6
7@a = common global i32 0
8
9define i32 @test_load() {
10entry:
11  %0 = load i32, i32* @a
12  ret i32 %0
13}
14
15; SMALL-LABEL: .test_load:{{$}}
16; SMALL: lwz [[REG1:[0-9]+]], L..C0(2)
17; SMALL: lwz [[REG2:[0-9]+]], 0([[REG1]])
18; SMALL: blr
19
20; LARGE-LABEL: .test_load:{{$}}
21; LARGE: addis [[REG1:[0-9]+]], L..C0@u(2)
22; LARGE: lwz [[REG2:[0-9]+]], L..C0@l([[REG1]])
23; LARGE: lwz [[REG3:[0-9]+]], 0([[REG2]])
24; LARGE: blr
25
26@b = common global i32 0
27
28define void @test_store(i32 %0) {
29  store i32 %0, i32* @b
30  ret void
31}
32
33; SMALL-LABEL: .test_store:{{$}}
34; SMALL: lwz [[REG1:[0-9]+]], L..C1(2)
35; SMALL: stw [[REG2:[0-9]+]], 0([[REG1]])
36; SMALL: blr
37
38; LARGE-LABEL: .test_store:{{$}}
39; LARGE: addis [[REG1:[0-9]+]], L..C1@u(2)
40; LARGE: lwz [[REG2:[0-9]+]], L..C1@l([[REG1]])
41; LARGE: stw [[REG3:[0-9]+]], 0([[REG2]])
42; LARGE: blr
43
44; SMALL: .tc a[TC],a
45; SMALL: .tc b[TC],b
46
47; LARGE: .tc a[TE],a
48; LARGE: .tc b[TE],b
49