1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ 3; RUN: -ppc-asm-full-reg-names -mcpu=pwr10 < %s | FileCheck %s \ 4; RUN: --check-prefixes=CHECK,CHECK-LE 5; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ 6; RUN: -ppc-asm-full-reg-names -mcpu=pwr10 < %s | FileCheck %s \ 7; RUN: --check-prefixes=CHECK,CHECK-BE 8 9; This file does not contain many test cases involving comparisons and logical 10; comparisons (cmplwi, cmpldi). This is because alternative code is generated 11; when there is a compare (logical or not), followed by a sign or zero extend. 12; This codegen will be re-evaluated at a later time on whether or not it should 13; be emitted on P10. 14 15@globalVal = common local_unnamed_addr global i8 0, align 1 16@globalVal2 = common local_unnamed_addr global i32 0, align 4 17@globalVal3 = common local_unnamed_addr global i64 0, align 8 18@globalVal4 = common local_unnamed_addr global i16 0, align 2 19 20define signext i32 @setbc1(i8 %a) { 21; CHECK-LABEL: setbc1: 22; CHECK: # %bb.0: # %entry 23; CHECK-NEXT: extsb r3, r3 24; CHECK-NEXT: cmpwi r3, 1 25; CHECK-NEXT: setbc r3, lt 26; CHECK-NEXT: blr 27entry: 28 %cmp = icmp slt i8 %a, 1 29 %conv = zext i1 %cmp to i32 30 ret i32 %conv 31} 32 33define signext i32 @setbc2(i32 %a) { 34; CHECK-LABEL: setbc2: 35; CHECK: # %bb.0: # %entry 36; CHECK-NEXT: cmpwi r3, 1 37; CHECK-NEXT: setbc r3, lt 38; CHECK-NEXT: blr 39entry: 40 %cmp = icmp slt i32 %a, 1 41 %conv = zext i1 %cmp to i32 42 ret i32 %conv 43} 44 45define signext i32 @setbc3(i64 %a) { 46; CHECK-LABEL: setbc3: 47; CHECK: # %bb.0: # %entry 48; CHECK-NEXT: cmpdi r3, 1 49; CHECK-NEXT: setbc r3, lt 50; CHECK-NEXT: blr 51entry: 52 %cmp = icmp slt i64 %a, 1 53 %conv = zext i1 %cmp to i32 54 ret i32 %conv 55} 56 57define signext i32 @setbc4(i16 %a) { 58; CHECK-LABEL: setbc4: 59; CHECK: # %bb.0: # %entry 60; CHECK-NEXT: extsh r3, r3 61; CHECK-NEXT: cmpwi r3, 1 62; CHECK-NEXT: setbc r3, lt 63; CHECK-NEXT: blr 64entry: 65 %cmp = icmp slt i16 %a, 1 66 %conv = zext i1 %cmp to i32 67 ret i32 %conv 68} 69 70define signext i64 @setbc5(i8 %a) { 71; CHECK-LABEL: setbc5: 72; CHECK: # %bb.0: # %entry 73; CHECK-NEXT: extsb r3, r3 74; CHECK-NEXT: cmpwi r3, 1 75; CHECK-NEXT: setbc r3, lt 76; CHECK-NEXT: blr 77entry: 78 %cmp = icmp slt i8 %a, 1 79 %conv = zext i1 %cmp to i64 80 ret i64 %conv 81} 82 83define signext i64 @setbc6(i32 %a) { 84; CHECK-LABEL: setbc6: 85; CHECK: # %bb.0: # %entry 86; CHECK-NEXT: cmpwi r3, 1 87; CHECK-NEXT: setbc r3, lt 88; CHECK-NEXT: blr 89entry: 90 %cmp = icmp slt i32 %a, 1 91 %conv = zext i1 %cmp to i64 92 ret i64 %conv 93} 94 95define signext i64 @setbc7(i64 %a) { 96; CHECK-LABEL: setbc7: 97; CHECK: # %bb.0: # %entry 98; CHECK-NEXT: cmpdi r3, 1 99; CHECK-NEXT: setbc r3, lt 100; CHECK-NEXT: blr 101entry: 102 %cmp = icmp slt i64 %a, 1 103 %conv = zext i1 %cmp to i64 104 ret i64 %conv 105} 106 107define signext i64 @setbc8(i16 %a) { 108; CHECK-LABEL: setbc8: 109; CHECK: # %bb.0: # %entry 110; CHECK-NEXT: extsh r3, r3 111; CHECK-NEXT: cmpwi r3, 1 112; CHECK-NEXT: setbc r3, lt 113; CHECK-NEXT: blr 114entry: 115 %cmp = icmp slt i16 %a, 1 116 %conv = zext i1 %cmp to i64 117 ret i64 %conv 118} 119 120define void @setbc9(i8 %a) { 121; CHECK-LE-LABEL: setbc9: 122; CHECK-LE: # %bb.0: # %entry 123; CHECK-LE-NEXT: extsb r3, r3 124; CHECK-LE-NEXT: cmpwi r3, 1 125; CHECK-LE-NEXT: setbc r3, lt 126; CHECK-LE-NEXT: pstb r3, globalVal@PCREL(0), 1 127; CHECK-LE-NEXT: blr 128; 129; CHECK-BE-LABEL: setbc9: 130; CHECK-BE: # %bb.0: # %entry 131; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha 132; CHECK-BE-NEXT: extsb r3, r3 133; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) 134; CHECK-BE-NEXT: cmpwi r3, 1 135; CHECK-BE-NEXT: setbc r3, lt 136; CHECK-BE-NEXT: stb r3, 0(r4) 137; CHECK-BE-NEXT: blr 138entry: 139 %cmp = icmp slt i8 %a, 1 140 %conv1 = zext i1 %cmp to i8 141 store i8 %conv1, i8* @globalVal, align 1 142 ret void 143} 144 145define void @setbc10(i32 %a) { 146; CHECK-LE-LABEL: setbc10: 147; CHECK-LE: # %bb.0: # %entry 148; CHECK-LE-NEXT: cmpwi r3, 1 149; CHECK-LE-NEXT: setbc r3, lt 150; CHECK-LE-NEXT: pstw r3, globalVal2@PCREL(0), 1 151; CHECK-LE-NEXT: blr 152; 153; CHECK-BE-LABEL: setbc10: 154; CHECK-BE: # %bb.0: # %entry 155; CHECK-BE-NEXT: addis r4, r2, .LC1@toc@ha 156; CHECK-BE-NEXT: cmpwi r3, 1 157; CHECK-BE-NEXT: ld r4, .LC1@toc@l(r4) 158; CHECK-BE-NEXT: setbc r3, lt 159; CHECK-BE-NEXT: stw r3, 0(r4) 160; CHECK-BE-NEXT: blr 161entry: 162 %cmp = icmp slt i32 %a, 1 163 %conv1 = zext i1 %cmp to i32 164 store i32 %conv1, i32* @globalVal2, align 4 165 ret void 166} 167 168define void @setbc11(i64 %a) { 169; CHECK-LE-LABEL: setbc11: 170; CHECK-LE: # %bb.0: # %entry 171; CHECK-LE-NEXT: cmpdi r3, 1 172; CHECK-LE-NEXT: setbc r3, lt 173; CHECK-LE-NEXT: pstd r3, globalVal3@PCREL(0), 1 174; CHECK-LE-NEXT: blr 175; 176; CHECK-BE-LABEL: setbc11: 177; CHECK-BE: # %bb.0: # %entry 178; CHECK-BE-NEXT: addis r4, r2, .LC2@toc@ha 179; CHECK-BE-NEXT: cmpdi r3, 1 180; CHECK-BE-NEXT: ld r4, .LC2@toc@l(r4) 181; CHECK-BE-NEXT: setbc r3, lt 182; CHECK-BE-NEXT: std r3, 0(r4) 183; CHECK-BE-NEXT: blr 184entry: 185 %cmp = icmp slt i64 %a, 1 186 %conv1 = zext i1 %cmp to i64 187 store i64 %conv1, i64* @globalVal3, align 8 188 ret void 189} 190 191define void @setbc12(i16 %a) { 192; CHECK-LE-LABEL: setbc12: 193; CHECK-LE: # %bb.0: # %entry 194; CHECK-LE-NEXT: extsh r3, r3 195; CHECK-LE-NEXT: cmpwi r3, 1 196; CHECK-LE-NEXT: setbc r3, lt 197; CHECK-LE-NEXT: psth r3, globalVal4@PCREL(0), 1 198; CHECK-LE-NEXT: blr 199; 200; CHECK-BE-LABEL: setbc12: 201; CHECK-BE: # %bb.0: # %entry 202; CHECK-BE-NEXT: addis r4, r2, .LC3@toc@ha 203; CHECK-BE-NEXT: extsh r3, r3 204; CHECK-BE-NEXT: ld r4, .LC3@toc@l(r4) 205; CHECK-BE-NEXT: cmpwi r3, 1 206; CHECK-BE-NEXT: setbc r3, lt 207; CHECK-BE-NEXT: sth r3, 0(r4) 208; CHECK-BE-NEXT: blr 209entry: 210 %cmp = icmp slt i16 %a, 1 211 %conv1 = zext i1 %cmp to i16 212 store i16 %conv1, i16* @globalVal4, align 2 213 ret void 214} 215 216define signext i32 @setbc13(i8 %a) { 217; CHECK-LABEL: setbc13: 218; CHECK: # %bb.0: # %entry 219; CHECK-NEXT: extsb r3, r3 220; CHECK-NEXT: cmpwi r3, 1 221; CHECK-NEXT: setbc r3, gt 222; CHECK-NEXT: blr 223entry: 224 %cmp = icmp sgt i8 %a, 1 225 %conv = zext i1 %cmp to i32 226 ret i32 %conv 227} 228 229define signext i32 @setbc14(i32 %a) { 230; CHECK-LABEL: setbc14: 231; CHECK: # %bb.0: # %entry 232; CHECK-NEXT: cmpwi r3, 1 233; CHECK-NEXT: setbc r3, gt 234; CHECK-NEXT: blr 235entry: 236 %cmp = icmp sgt i32 %a, 1 237 %conv = zext i1 %cmp to i32 238 ret i32 %conv 239} 240 241define signext i32 @setbc15(i64 %a) { 242; CHECK-LABEL: setbc15: 243; CHECK: # %bb.0: # %entry 244; CHECK-NEXT: cmpdi r3, 1 245; CHECK-NEXT: setbc r3, gt 246; CHECK-NEXT: blr 247entry: 248 %cmp = icmp sgt i64 %a, 1 249 %conv = zext i1 %cmp to i32 250 ret i32 %conv 251} 252 253define signext i32 @setbc16(i16 %a) { 254; CHECK-LABEL: setbc16: 255; CHECK: # %bb.0: # %entry 256; CHECK-NEXT: extsh r3, r3 257; CHECK-NEXT: cmpwi r3, 1 258; CHECK-NEXT: setbc r3, gt 259; CHECK-NEXT: blr 260entry: 261 %cmp = icmp sgt i16 %a, 1 262 %conv = zext i1 %cmp to i32 263 ret i32 %conv 264} 265 266define signext i64 @setbc17(i8 %a) { 267; CHECK-LABEL: setbc17: 268; CHECK: # %bb.0: # %entry 269; CHECK-NEXT: extsb r3, r3 270; CHECK-NEXT: cmpwi r3, 1 271; CHECK-NEXT: setbc r3, gt 272; CHECK-NEXT: blr 273entry: 274 %cmp = icmp sgt i8 %a, 1 275 %conv = zext i1 %cmp to i64 276 ret i64 %conv 277} 278 279define signext i64 @setbc18(i32 %a) { 280; CHECK-LABEL: setbc18: 281; CHECK: # %bb.0: # %entry 282; CHECK-NEXT: cmpwi r3, 1 283; CHECK-NEXT: setbc r3, gt 284; CHECK-NEXT: blr 285entry: 286 %cmp = icmp sgt i32 %a, 1 287 %conv = zext i1 %cmp to i64 288 ret i64 %conv 289} 290 291define signext i64 @setbc19(i64 %a) { 292; CHECK-LABEL: setbc19: 293; CHECK: # %bb.0: # %entry 294; CHECK-NEXT: cmpdi r3, 1 295; CHECK-NEXT: setbc r3, gt 296; CHECK-NEXT: blr 297entry: 298 %cmp = icmp sgt i64 %a, 1 299 %conv = zext i1 %cmp to i64 300 ret i64 %conv 301} 302 303define signext i64 @setbc20(i16 %a) { 304; CHECK-LABEL: setbc20: 305; CHECK: # %bb.0: # %entry 306; CHECK-NEXT: extsh r3, r3 307; CHECK-NEXT: cmpwi r3, 1 308; CHECK-NEXT: setbc r3, gt 309; CHECK-NEXT: blr 310entry: 311 %cmp = icmp sgt i16 %a, 1 312 %conv = zext i1 %cmp to i64 313 ret i64 %conv 314} 315 316define void @setbc21(i8 %a) { 317; CHECK-LE-LABEL: setbc21: 318; CHECK-LE: # %bb.0: # %entry 319; CHECK-LE-NEXT: extsb r3, r3 320; CHECK-LE-NEXT: cmpwi r3, 1 321; CHECK-LE-NEXT: setbc r3, gt 322; CHECK-LE-NEXT: pstb r3, globalVal@PCREL(0), 1 323; CHECK-LE-NEXT: blr 324; 325; CHECK-BE-LABEL: setbc21: 326; CHECK-BE: # %bb.0: # %entry 327; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha 328; CHECK-BE-NEXT: extsb r3, r3 329; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) 330; CHECK-BE-NEXT: cmpwi r3, 1 331; CHECK-BE-NEXT: setbc r3, gt 332; CHECK-BE-NEXT: stb r3, 0(r4) 333; CHECK-BE-NEXT: blr 334entry: 335 %cmp = icmp sgt i8 %a, 1 336 %conv1 = zext i1 %cmp to i8 337 store i8 %conv1, i8* @globalVal, align 1 338 ret void 339} 340 341define void @setbc22(i32 %a) { 342; CHECK-LE-LABEL: setbc22: 343; CHECK-LE: # %bb.0: # %entry 344; CHECK-LE-NEXT: cmpwi r3, 1 345; CHECK-LE-NEXT: setbc r3, gt 346; CHECK-LE-NEXT: pstw r3, globalVal2@PCREL(0), 1 347; CHECK-LE-NEXT: blr 348; 349; CHECK-BE-LABEL: setbc22: 350; CHECK-BE: # %bb.0: # %entry 351; CHECK-BE-NEXT: addis r4, r2, .LC1@toc@ha 352; CHECK-BE-NEXT: cmpwi r3, 1 353; CHECK-BE-NEXT: ld r4, .LC1@toc@l(r4) 354; CHECK-BE-NEXT: setbc r3, gt 355; CHECK-BE-NEXT: stw r3, 0(r4) 356; CHECK-BE-NEXT: blr 357entry: 358 %cmp = icmp sgt i32 %a, 1 359 %conv1 = zext i1 %cmp to i32 360 store i32 %conv1, i32* @globalVal2, align 4 361 ret void 362} 363 364define void @setbc23(i64 %a) { 365; CHECK-LE-LABEL: setbc23: 366; CHECK-LE: # %bb.0: # %entry 367; CHECK-LE-NEXT: cmpdi r3, 1 368; CHECK-LE-NEXT: setbc r3, gt 369; CHECK-LE-NEXT: pstd r3, globalVal3@PCREL(0), 1 370; CHECK-LE-NEXT: blr 371; 372; CHECK-BE-LABEL: setbc23: 373; CHECK-BE: # %bb.0: # %entry 374; CHECK-BE-NEXT: addis r4, r2, .LC2@toc@ha 375; CHECK-BE-NEXT: cmpdi r3, 1 376; CHECK-BE-NEXT: ld r4, .LC2@toc@l(r4) 377; CHECK-BE-NEXT: setbc r3, gt 378; CHECK-BE-NEXT: std r3, 0(r4) 379; CHECK-BE-NEXT: blr 380entry: 381 %cmp = icmp sgt i64 %a, 1 382 %conv1 = zext i1 %cmp to i64 383 store i64 %conv1, i64* @globalVal3, align 8 384 ret void 385} 386 387define void @setbc24(i16 %a) { 388; CHECK-LE-LABEL: setbc24: 389; CHECK-LE: # %bb.0: # %entry 390; CHECK-LE-NEXT: extsh r3, r3 391; CHECK-LE-NEXT: cmpwi r3, 1 392; CHECK-LE-NEXT: setbc r3, gt 393; CHECK-LE-NEXT: psth r3, globalVal4@PCREL(0), 1 394; CHECK-LE-NEXT: blr 395; 396; CHECK-BE-LABEL: setbc24: 397; CHECK-BE: # %bb.0: # %entry 398; CHECK-BE-NEXT: addis r4, r2, .LC3@toc@ha 399; CHECK-BE-NEXT: extsh r3, r3 400; CHECK-BE-NEXT: ld r4, .LC3@toc@l(r4) 401; CHECK-BE-NEXT: cmpwi r3, 1 402; CHECK-BE-NEXT: setbc r3, gt 403; CHECK-BE-NEXT: sth r3, 0(r4) 404; CHECK-BE-NEXT: blr 405entry: 406 %cmp = icmp sgt i16 %a, 1 407 %conv1 = zext i1 %cmp to i16 408 store i16 %conv1, i16* @globalVal4, align 2 409 ret void 410} 411 412define signext i32 @setbc25(i8 %a) { 413; CHECK-LABEL: setbc25: 414; CHECK: # %bb.0: # %entry 415; CHECK-NEXT: clrlwi r3, r3, 24 416; CHECK-NEXT: cmpwi r3, 1 417; CHECK-NEXT: setbc r3, eq 418; CHECK-NEXT: blr 419entry: 420 %cmp = icmp eq i8 %a, 1 421 %conv = zext i1 %cmp to i32 422 ret i32 %conv 423} 424 425define signext i32 @setbc26(i32 %a) { 426; CHECK-LABEL: setbc26: 427; CHECK: # %bb.0: # %entry 428; CHECK-NEXT: cmpwi r3, 1 429; CHECK-NEXT: setbc r3, eq 430; CHECK-NEXT: blr 431entry: 432 %cmp = icmp eq i32 %a, 1 433 %conv = zext i1 %cmp to i32 434 ret i32 %conv 435} 436 437define signext i32 @setbc27(i64 %a) { 438; CHECK-LABEL: setbc27: 439; CHECK: # %bb.0: # %entry 440; CHECK-NEXT: cmpdi r3, 1 441; CHECK-NEXT: setbc r3, eq 442; CHECK-NEXT: blr 443entry: 444 %cmp = icmp eq i64 %a, 1 445 %conv = zext i1 %cmp to i32 446 ret i32 %conv 447} 448 449define signext i32 @setbc28(i16 %a) { 450; CHECK-LABEL: setbc28: 451; CHECK: # %bb.0: # %entry 452; CHECK-NEXT: clrlwi r3, r3, 16 453; CHECK-NEXT: cmpwi r3, 1 454; CHECK-NEXT: setbc r3, eq 455; CHECK-NEXT: blr 456entry: 457 %cmp = icmp eq i16 %a, 1 458 %conv = zext i1 %cmp to i32 459 ret i32 %conv 460} 461 462define signext i64 @setbc29(i8 %a) { 463; CHECK-LABEL: setbc29: 464; CHECK: # %bb.0: # %entry 465; CHECK-NEXT: clrlwi r3, r3, 24 466; CHECK-NEXT: cmpwi r3, 1 467; CHECK-NEXT: setbc r3, eq 468; CHECK-NEXT: blr 469entry: 470 %cmp = icmp eq i8 %a, 1 471 %conv = zext i1 %cmp to i64 472 ret i64 %conv 473} 474 475define signext i64 @setbc30(i32 %a) { 476; CHECK-LABEL: setbc30: 477; CHECK: # %bb.0: # %entry 478; CHECK-NEXT: cmpwi r3, 1 479; CHECK-NEXT: setbc r3, eq 480; CHECK-NEXT: blr 481entry: 482 %cmp = icmp eq i32 %a, 1 483 %conv = zext i1 %cmp to i64 484 ret i64 %conv 485} 486 487define signext i64 @setbc31(i64 %a) { 488; CHECK-LABEL: setbc31: 489; CHECK: # %bb.0: # %entry 490; CHECK-NEXT: cmpdi r3, 1 491; CHECK-NEXT: setbc r3, eq 492; CHECK-NEXT: blr 493entry: 494 %cmp = icmp eq i64 %a, 1 495 %conv = zext i1 %cmp to i64 496 ret i64 %conv 497} 498 499define signext i64 @setbc32(i16 %a) { 500; CHECK-LABEL: setbc32: 501; CHECK: # %bb.0: # %entry 502; CHECK-NEXT: clrlwi r3, r3, 16 503; CHECK-NEXT: cmpwi r3, 1 504; CHECK-NEXT: setbc r3, eq 505; CHECK-NEXT: blr 506entry: 507 %cmp = icmp eq i16 %a, 1 508 %conv = zext i1 %cmp to i64 509 ret i64 %conv 510} 511 512define void @setbc33(i8 %a) { 513; CHECK-LE-LABEL: setbc33: 514; CHECK-LE: # %bb.0: # %entry 515; CHECK-LE-NEXT: clrlwi r3, r3, 24 516; CHECK-LE-NEXT: cmpwi r3, 1 517; CHECK-LE-NEXT: setbc r3, eq 518; CHECK-LE-NEXT: pstb r3, globalVal@PCREL(0), 1 519; CHECK-LE-NEXT: blr 520; 521; CHECK-BE-LABEL: setbc33: 522; CHECK-BE: # %bb.0: # %entry 523; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha 524; CHECK-BE-NEXT: clrlwi r3, r3, 24 525; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) 526; CHECK-BE-NEXT: cmpwi r3, 1 527; CHECK-BE-NEXT: setbc r3, eq 528; CHECK-BE-NEXT: stb r3, 0(r4) 529; CHECK-BE-NEXT: blr 530entry: 531 %cmp = icmp eq i8 %a, 1 532 %conv1 = zext i1 %cmp to i8 533 store i8 %conv1, i8* @globalVal, align 1 534 ret void 535} 536 537define void @setbc34(i32 %a) { 538; CHECK-LE-LABEL: setbc34: 539; CHECK-LE: # %bb.0: # %entry 540; CHECK-LE-NEXT: cmpwi r3, 1 541; CHECK-LE-NEXT: setbc r3, eq 542; CHECK-LE-NEXT: pstw r3, globalVal2@PCREL(0), 1 543; CHECK-LE-NEXT: blr 544; 545; CHECK-BE-LABEL: setbc34: 546; CHECK-BE: # %bb.0: # %entry 547; CHECK-BE-NEXT: addis r4, r2, .LC1@toc@ha 548; CHECK-BE-NEXT: cmpwi r3, 1 549; CHECK-BE-NEXT: ld r4, .LC1@toc@l(r4) 550; CHECK-BE-NEXT: setbc r3, eq 551; CHECK-BE-NEXT: stw r3, 0(r4) 552; CHECK-BE-NEXT: blr 553entry: 554 %cmp = icmp eq i32 %a, 1 555 %conv1 = zext i1 %cmp to i32 556 store i32 %conv1, i32* @globalVal2, align 4 557 ret void 558} 559 560define void @setbc35(i64 %a) { 561; CHECK-LE-LABEL: setbc35: 562; CHECK-LE: # %bb.0: # %entry 563; CHECK-LE-NEXT: cmpdi r3, 1 564; CHECK-LE-NEXT: setbc r3, eq 565; CHECK-LE-NEXT: pstd r3, globalVal3@PCREL(0), 1 566; CHECK-LE-NEXT: blr 567; 568; CHECK-BE-LABEL: setbc35: 569; CHECK-BE: # %bb.0: # %entry 570; CHECK-BE-NEXT: addis r4, r2, .LC2@toc@ha 571; CHECK-BE-NEXT: cmpdi r3, 1 572; CHECK-BE-NEXT: ld r4, .LC2@toc@l(r4) 573; CHECK-BE-NEXT: setbc r3, eq 574; CHECK-BE-NEXT: std r3, 0(r4) 575; CHECK-BE-NEXT: blr 576entry: 577 %cmp = icmp eq i64 %a, 1 578 %conv1 = zext i1 %cmp to i64 579 store i64 %conv1, i64* @globalVal3, align 8 580 ret void 581} 582 583define void @setbc36(i16 %a) { 584; CHECK-LE-LABEL: setbc36: 585; CHECK-LE: # %bb.0: # %entry 586; CHECK-LE-NEXT: clrlwi r3, r3, 16 587; CHECK-LE-NEXT: cmpwi r3, 1 588; CHECK-LE-NEXT: setbc r3, eq 589; CHECK-LE-NEXT: psth r3, globalVal4@PCREL(0), 1 590; CHECK-LE-NEXT: blr 591; 592; CHECK-BE-LABEL: setbc36: 593; CHECK-BE: # %bb.0: # %entry 594; CHECK-BE-NEXT: addis r4, r2, .LC3@toc@ha 595; CHECK-BE-NEXT: clrlwi r3, r3, 16 596; CHECK-BE-NEXT: ld r4, .LC3@toc@l(r4) 597; CHECK-BE-NEXT: cmpwi r3, 1 598; CHECK-BE-NEXT: setbc r3, eq 599; CHECK-BE-NEXT: sth r3, 0(r4) 600; CHECK-BE-NEXT: blr 601entry: 602 %cmp = icmp eq i16 %a, 1 603 %conv1 = zext i1 %cmp to i16 604 store i16 %conv1, i16* @globalVal4, align 2 605 ret void 606} 607 608define signext i32 @setbc37(i64 %a) { 609; CHECK-LABEL: setbc37: 610; CHECK: # %bb.0: # %entry 611; CHECK-NEXT: cmpldi r3, 1 612; CHECK-NEXT: setbc r3, gt 613; CHECK-NEXT: blr 614entry: 615 %cmp = icmp ugt i64 %a, 1 616 %conv = zext i1 %cmp to i32 617 ret i32 %conv 618} 619 620define signext i64 @setbc38(i64 %a) { 621; CHECK-LABEL: setbc38: 622; CHECK: # %bb.0: # %entry 623; CHECK-NEXT: cmpldi r3, 1 624; CHECK-NEXT: setbc r3, gt 625; CHECK-NEXT: blr 626entry: 627 %cmp = icmp ugt i64 %a, 1 628 %conv = zext i1 %cmp to i64 629 ret i64 %conv 630} 631 632define void @setbc39(i64 %a) { 633; CHECK-LE-LABEL: setbc39: 634; CHECK-LE: # %bb.0: # %entry 635; CHECK-LE-NEXT: cmpldi r3, 1 636; CHECK-LE-NEXT: setbc r3, gt 637; CHECK-LE-NEXT: pstd r3, globalVal3@PCREL(0), 1 638; CHECK-LE-NEXT: blr 639; 640; CHECK-BE-LABEL: setbc39: 641; CHECK-BE: # %bb.0: # %entry 642; CHECK-BE-NEXT: addis r4, r2, .LC2@toc@ha 643; CHECK-BE-NEXT: cmpldi r3, 1 644; CHECK-BE-NEXT: ld r4, .LC2@toc@l(r4) 645; CHECK-BE-NEXT: setbc r3, gt 646; CHECK-BE-NEXT: std r3, 0(r4) 647; CHECK-BE-NEXT: blr 648entry: 649 %cmp = icmp ugt i64 %a, 1 650 %conv1 = zext i1 %cmp to i64 651 store i64 %conv1, i64* @globalVal3, align 8 652 ret void 653} 654