1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
3; RUN:     -ppc-asm-full-reg-names -mcpu=pwr10 < %s | FileCheck %s \
4; RUN:     --check-prefixes=CHECK,CHECK-LE
5; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
6; RUN:     -ppc-asm-full-reg-names -mcpu=pwr10 < %s | FileCheck %s \
7; RUN:     --check-prefixes=CHECK,CHECK-BE
8
9; This file does not contain many test cases involving comparisons and logical
10; comparisons (cmplwi, cmpldi). This is because alternative code is generated
11; when there is a compare (logical or not), followed by a sign or zero extend.
12; This codegen will be re-evaluated at a later time on whether or not it should
13; be emitted on P10.
14
15@globalVal = common local_unnamed_addr global i8 0, align 1
16@globalVal2 = common local_unnamed_addr global i32 0, align 4
17@globalVal3 = common local_unnamed_addr global i64 0, align 8
18@globalVal4 = common local_unnamed_addr global i16 0, align 2
19
20define signext i32 @setbc1(i32 signext %a, i32 signext %b) {
21; CHECK-LABEL: setbc1:
22; CHECK:       # %bb.0: # %entry
23; CHECK-NEXT:    cmpw r3, r4
24; CHECK-NEXT:    setbc r3, lt
25; CHECK-NEXT:    blr
26entry:
27  %cmp = icmp slt i32 %a, %b
28  %conv = zext i1 %cmp to i32
29  ret i32 %conv
30}
31
32define signext i32 @setbc2(i32 signext %a, i32 signext %b) {
33; CHECK-LABEL: setbc2:
34; CHECK:       # %bb.0: # %entry
35; CHECK-NEXT:    cmpw r3, r4
36; CHECK-NEXT:    setbc r3, eq
37; CHECK-NEXT:    blr
38entry:
39  %cmp = icmp eq i32 %a, %b
40  %conv = zext i1 %cmp to i32
41  ret i32 %conv
42}
43
44define signext i32 @setbc3(i32 signext %a, i32 signext %b) {
45; CHECK-LABEL: setbc3:
46; CHECK:       # %bb.0: # %entry
47; CHECK-NEXT:    cmpw r3, r4
48; CHECK-NEXT:    setbc r3, gt
49; CHECK-NEXT:    blr
50entry:
51  %cmp = icmp sgt i32 %a, %b
52  %conv = zext i1 %cmp to i32
53  ret i32 %conv
54}
55
56define signext i32 @setbc4(i8 signext %a, i8 signext %b) {
57; CHECK-LABEL: setbc4:
58; CHECK:       # %bb.0: # %entry
59; CHECK-NEXT:    cmpw r3, r4
60; CHECK-NEXT:    setbc r3, eq
61; CHECK-NEXT:    blr
62entry:
63  %cmp = icmp eq i8 %a, %b
64  %conv2 = zext i1 %cmp to i32
65  ret i32 %conv2
66}
67
68define void @setbc5(i8 signext %a, i8 signext %b) {
69; CHECK-LE-LABEL: setbc5:
70; CHECK-LE:       # %bb.0: # %entry
71; CHECK-LE-NEXT:    cmpw r3, r4
72; CHECK-LE-NEXT:    setbc r3, eq
73; CHECK-LE-NEXT:    pstb r3, globalVal@PCREL(0), 1
74; CHECK-LE-NEXT:    blr
75;
76; CHECK-BE-LABEL: setbc5:
77; CHECK-BE:       # %bb.0: # %entry
78; CHECK-BE-NEXT:    cmpw r3, r4
79; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
80; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
81; CHECK-BE-NEXT:    setbc r3, eq
82; CHECK-BE-NEXT:    stb r3, 0(r4)
83; CHECK-BE-NEXT:    blr
84entry:
85  %cmp = icmp eq i8 %a, %b
86  %conv3 = zext i1 %cmp to i8
87  store i8 %conv3, i8* @globalVal, align 1
88  ret void
89}
90
91define void @setbc6(i32 signext %a, i32 signext %b) {
92; CHECK-LE-LABEL: setbc6:
93; CHECK-LE:       # %bb.0: # %entry
94; CHECK-LE-NEXT:    cmpw r3, r4
95; CHECK-LE-NEXT:    setbc r3, eq
96; CHECK-LE-NEXT:    pstw r3, globalVal2@PCREL(0), 1
97; CHECK-LE-NEXT:    blr
98;
99; CHECK-BE-LABEL: setbc6:
100; CHECK-BE:       # %bb.0: # %entry
101; CHECK-BE-NEXT:    cmpw r3, r4
102; CHECK-BE-NEXT:    addis r4, r2, .LC1@toc@ha
103; CHECK-BE-NEXT:    ld r4, .LC1@toc@l(r4)
104; CHECK-BE-NEXT:    setbc r3, eq
105; CHECK-BE-NEXT:    stw r3, 0(r4)
106; CHECK-BE-NEXT:    blr
107entry:
108  %cmp = icmp eq i32 %a, %b
109  %conv = zext i1 %cmp to i32
110  store i32 %conv, i32* @globalVal2, align 4
111  ret void
112}
113
114define signext i32 @setbc7(i64 %a, i64 %b) {
115; CHECK-LABEL: setbc7:
116; CHECK:       # %bb.0: # %entry
117; CHECK-NEXT:    cmpd r3, r4
118; CHECK-NEXT:    setbc r3, eq
119; CHECK-NEXT:    blr
120entry:
121  %cmp = icmp eq i64 %a, %b
122  %conv = zext i1 %cmp to i32
123  ret i32 %conv
124}
125
126define signext i64 @setbc8(i64 %a, i64 %b) {
127; CHECK-LABEL: setbc8:
128; CHECK:       # %bb.0: # %entry
129; CHECK-NEXT:    cmpd r3, r4
130; CHECK-NEXT:    setbc r3, eq
131; CHECK-NEXT:    blr
132entry:
133  %cmp = icmp eq i64 %a, %b
134  %conv = zext i1 %cmp to i64
135  ret i64 %conv
136}
137
138
139define void @setbc9(i64 %a, i64 %b) {
140; CHECK-LE-LABEL: setbc9:
141; CHECK-LE:       # %bb.0: # %entry
142; CHECK-LE-NEXT:    cmpd r3, r4
143; CHECK-LE-NEXT:    setbc r3, eq
144; CHECK-LE-NEXT:    pstd r3, globalVal3@PCREL(0), 1
145; CHECK-LE-NEXT:    blr
146;
147; CHECK-BE-LABEL: setbc9:
148; CHECK-BE:       # %bb.0: # %entry
149; CHECK-BE-NEXT:    cmpd r3, r4
150; CHECK-BE-NEXT:    addis r4, r2, .LC2@toc@ha
151; CHECK-BE-NEXT:    ld r4, .LC2@toc@l(r4)
152; CHECK-BE-NEXT:    setbc r3, eq
153; CHECK-BE-NEXT:    std r3, 0(r4)
154; CHECK-BE-NEXT:    blr
155entry:
156  %cmp = icmp eq i64 %a, %b
157  %conv1 = zext i1 %cmp to i64
158  store i64 %conv1, i64* @globalVal3, align 8
159  ret void
160}
161
162
163define signext i32 @setbc10(i16 signext %a, i16 signext %b) {
164; CHECK-LABEL: setbc10:
165; CHECK:       # %bb.0: # %entry
166; CHECK-NEXT:    cmpw r3, r4
167; CHECK-NEXT:    setbc r3, eq
168; CHECK-NEXT:    blr
169entry:
170  %cmp = icmp eq i16 %a, %b
171  %conv2 = zext i1 %cmp to i32
172  ret i32 %conv2
173}
174
175
176define void @setbc11(i16 signext %a, i16 signext %b) {
177; CHECK-LE-LABEL: setbc11:
178; CHECK-LE:       # %bb.0: # %entry
179; CHECK-LE-NEXT:    cmpw r3, r4
180; CHECK-LE-NEXT:    setbc r3, eq
181; CHECK-LE-NEXT:    psth r3, globalVal4@PCREL(0), 1
182; CHECK-LE-NEXT:    blr
183;
184; CHECK-BE-LABEL: setbc11:
185; CHECK-BE:       # %bb.0: # %entry
186; CHECK-BE-NEXT:    cmpw r3, r4
187; CHECK-BE-NEXT:    addis r4, r2, .LC3@toc@ha
188; CHECK-BE-NEXT:    ld r4, .LC3@toc@l(r4)
189; CHECK-BE-NEXT:    setbc r3, eq
190; CHECK-BE-NEXT:    sth r3, 0(r4)
191; CHECK-BE-NEXT:    blr
192entry:
193  %cmp = icmp eq i16 %a, %b
194  %conv3 = zext i1 %cmp to i16
195  store i16 %conv3, i16* @globalVal4, align 2
196  ret void
197}
198
199
200define signext i32 @setbc12(i8 zeroext %a, i8 zeroext %b) {
201; CHECK-LABEL: setbc12:
202; CHECK:       # %bb.0: # %entry
203; CHECK-NEXT:    cmpw r3, r4
204; CHECK-NEXT:    setbc r3, eq
205; CHECK-NEXT:    blr
206entry:
207  %cmp = icmp eq i8 %a, %b
208  %conv2 = zext i1 %cmp to i32
209  ret i32 %conv2
210}
211
212
213define void @setbc13(i8 zeroext %a, i8 zeroext %b) {
214; CHECK-LE-LABEL: setbc13:
215; CHECK-LE:       # %bb.0: # %entry
216; CHECK-LE-NEXT:    cmpw r3, r4
217; CHECK-LE-NEXT:    setbc r3, eq
218; CHECK-LE-NEXT:    pstb r3, globalVal@PCREL(0), 1
219; CHECK-LE-NEXT:    blr
220;
221; CHECK-BE-LABEL: setbc13:
222; CHECK-BE:       # %bb.0: # %entry
223; CHECK-BE-NEXT:    cmpw r3, r4
224; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
225; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
226; CHECK-BE-NEXT:    setbc r3, eq
227; CHECK-BE-NEXT:    stb r3, 0(r4)
228; CHECK-BE-NEXT:    blr
229entry:
230  %cmp = icmp eq i8 %a, %b
231  %conv3 = zext i1 %cmp to i8
232  store i8 %conv3, i8* @globalVal, align 1
233  ret void
234}
235
236
237define signext i32 @setbc14(i32 zeroext %a, i32 zeroext %b) {
238; CHECK-LABEL: setbc14:
239; CHECK:       # %bb.0: # %entry
240; CHECK-NEXT:    cmpw r3, r4
241; CHECK-NEXT:    setbc r3, eq
242; CHECK-NEXT:    blr
243entry:
244  %cmp = icmp eq i32 %a, %b
245  %conv = zext i1 %cmp to i32
246  ret i32 %conv
247}
248
249
250define void @setbc15(i32 zeroext %a, i32 zeroext %b) {
251; CHECK-LE-LABEL: setbc15:
252; CHECK-LE:       # %bb.0: # %entry
253; CHECK-LE-NEXT:    cmpw r3, r4
254; CHECK-LE-NEXT:    setbc r3, eq
255; CHECK-LE-NEXT:    pstw r3, globalVal2@PCREL(0), 1
256; CHECK-LE-NEXT:    blr
257;
258; CHECK-BE-LABEL: setbc15:
259; CHECK-BE:       # %bb.0: # %entry
260; CHECK-BE-NEXT:    cmpw r3, r4
261; CHECK-BE-NEXT:    addis r4, r2, .LC1@toc@ha
262; CHECK-BE-NEXT:    ld r4, .LC1@toc@l(r4)
263; CHECK-BE-NEXT:    setbc r3, eq
264; CHECK-BE-NEXT:    stw r3, 0(r4)
265; CHECK-BE-NEXT:    blr
266entry:
267  %cmp = icmp eq i32 %a, %b
268  %conv = zext i1 %cmp to i32
269  store i32 %conv, i32* @globalVal2, align 4
270  ret void
271}
272
273
274define signext i32 @setbc16(i16 zeroext %a, i16 zeroext %b) {
275; CHECK-LABEL: setbc16:
276; CHECK:       # %bb.0: # %entry
277; CHECK-NEXT:    cmpw r3, r4
278; CHECK-NEXT:    setbc r3, eq
279; CHECK-NEXT:    blr
280entry:
281  %cmp = icmp eq i16 %a, %b
282  %conv2 = zext i1 %cmp to i32
283  ret i32 %conv2
284}
285
286
287define void @setbc17(i16 zeroext %a, i16 zeroext %b) {
288; CHECK-LE-LABEL: setbc17:
289; CHECK-LE:       # %bb.0: # %entry
290; CHECK-LE-NEXT:    cmpw r3, r4
291; CHECK-LE-NEXT:    setbc r3, eq
292; CHECK-LE-NEXT:    psth r3, globalVal4@PCREL(0), 1
293; CHECK-LE-NEXT:    blr
294;
295; CHECK-BE-LABEL: setbc17:
296; CHECK-BE:       # %bb.0: # %entry
297; CHECK-BE-NEXT:    cmpw r3, r4
298; CHECK-BE-NEXT:    addis r4, r2, .LC3@toc@ha
299; CHECK-BE-NEXT:    ld r4, .LC3@toc@l(r4)
300; CHECK-BE-NEXT:    setbc r3, eq
301; CHECK-BE-NEXT:    sth r3, 0(r4)
302; CHECK-BE-NEXT:    blr
303entry:
304  %cmp = icmp eq i16 %a, %b
305  %conv3 = zext i1 %cmp to i16
306  store i16 %conv3, i16* @globalVal4, align 2
307  ret void
308}
309
310
311define signext i32 @setbc18(i8 signext %a, i8 signext %b) {
312; CHECK-LABEL: setbc18:
313; CHECK:       # %bb.0: # %entry
314; CHECK-NEXT:    cmpw r3, r4
315; CHECK-NEXT:    setbc r3, gt
316; CHECK-NEXT:    blr
317entry:
318  %cmp = icmp sgt i8 %a, %b
319  %conv2 = zext i1 %cmp to i32
320  ret i32 %conv2
321}
322
323
324define void @setbc19(i8 signext %a, i8 signext %b) {
325; CHECK-LE-LABEL: setbc19:
326; CHECK-LE:       # %bb.0: # %entry
327; CHECK-LE-NEXT:    cmpw r3, r4
328; CHECK-LE-NEXT:    setbc r3, gt
329; CHECK-LE-NEXT:    pstb r3, globalVal@PCREL(0), 1
330; CHECK-LE-NEXT:    blr
331;
332; CHECK-BE-LABEL: setbc19:
333; CHECK-BE:       # %bb.0: # %entry
334; CHECK-BE-NEXT:    cmpw r3, r4
335; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
336; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
337; CHECK-BE-NEXT:    setbc r3, gt
338; CHECK-BE-NEXT:    stb r3, 0(r4)
339; CHECK-BE-NEXT:    blr
340entry:
341  %cmp = icmp sgt i8 %a, %b
342  %conv3 = zext i1 %cmp to i8
343  store i8 %conv3, i8* @globalVal, align 1
344  ret void
345}
346
347
348define void @setbc20(i32 signext %a, i32 signext %b) {
349; CHECK-LE-LABEL: setbc20:
350; CHECK-LE:       # %bb.0: # %entry
351; CHECK-LE-NEXT:    cmpw r3, r4
352; CHECK-LE-NEXT:    setbc r3, gt
353; CHECK-LE-NEXT:    pstw r3, globalVal2@PCREL(0), 1
354; CHECK-LE-NEXT:    blr
355;
356; CHECK-BE-LABEL: setbc20:
357; CHECK-BE:       # %bb.0: # %entry
358; CHECK-BE-NEXT:    cmpw r3, r4
359; CHECK-BE-NEXT:    addis r4, r2, .LC1@toc@ha
360; CHECK-BE-NEXT:    ld r4, .LC1@toc@l(r4)
361; CHECK-BE-NEXT:    setbc r3, gt
362; CHECK-BE-NEXT:    stw r3, 0(r4)
363; CHECK-BE-NEXT:    blr
364entry:
365  %cmp = icmp sgt i32 %a, %b
366  %conv = zext i1 %cmp to i32
367  store i32 %conv, i32* @globalVal2, align 4
368  ret void
369}
370
371
372define signext i32 @setbc21(i64 %a, i64 %b) {
373; CHECK-LABEL: setbc21:
374; CHECK:       # %bb.0: # %entry
375; CHECK-NEXT:    cmpd r3, r4
376; CHECK-NEXT:    setbc r3, gt
377; CHECK-NEXT:    blr
378entry:
379  %cmp = icmp sgt i64 %a, %b
380  %conv = zext i1 %cmp to i32
381  ret i32 %conv
382}
383
384
385define void @setbc22(i64 %a, i64 %b) {
386; CHECK-LE-LABEL: setbc22:
387; CHECK-LE:       # %bb.0: # %entry
388; CHECK-LE-NEXT:    cmpd r3, r4
389; CHECK-LE-NEXT:    setbc r3, gt
390; CHECK-LE-NEXT:    pstd r3, globalVal3@PCREL(0), 1
391; CHECK-LE-NEXT:    blr
392;
393; CHECK-BE-LABEL: setbc22:
394; CHECK-BE:       # %bb.0: # %entry
395; CHECK-BE-NEXT:    cmpd r3, r4
396; CHECK-BE-NEXT:    addis r4, r2, .LC2@toc@ha
397; CHECK-BE-NEXT:    ld r4, .LC2@toc@l(r4)
398; CHECK-BE-NEXT:    setbc r3, gt
399; CHECK-BE-NEXT:    std r3, 0(r4)
400; CHECK-BE-NEXT:    blr
401entry:
402  %cmp = icmp sgt i64 %a, %b
403  %conv1 = zext i1 %cmp to i64
404  store i64 %conv1, i64* @globalVal3, align 8
405  ret void
406}
407
408
409define signext i32 @setbc23(i16 signext %a, i16 signext %b) {
410; CHECK-LABEL: setbc23:
411; CHECK:       # %bb.0: # %entry
412; CHECK-NEXT:    cmpw r3, r4
413; CHECK-NEXT:    setbc r3, gt
414; CHECK-NEXT:    blr
415entry:
416  %cmp = icmp sgt i16 %a, %b
417  %conv2 = zext i1 %cmp to i32
418  ret i32 %conv2
419}
420
421
422define void @setbc24(i16 signext %a, i16 signext %b) {
423; CHECK-LE-LABEL: setbc24:
424; CHECK-LE:       # %bb.0: # %entry
425; CHECK-LE-NEXT:    cmpw r3, r4
426; CHECK-LE-NEXT:    setbc r3, gt
427; CHECK-LE-NEXT:    psth r3, globalVal4@PCREL(0), 1
428; CHECK-LE-NEXT:    blr
429;
430; CHECK-BE-LABEL: setbc24:
431; CHECK-BE:       # %bb.0: # %entry
432; CHECK-BE-NEXT:    cmpw r3, r4
433; CHECK-BE-NEXT:    addis r4, r2, .LC3@toc@ha
434; CHECK-BE-NEXT:    ld r4, .LC3@toc@l(r4)
435; CHECK-BE-NEXT:    setbc r3, gt
436; CHECK-BE-NEXT:    sth r3, 0(r4)
437; CHECK-BE-NEXT:    blr
438entry:
439  %cmp = icmp sgt i16 %a, %b
440  %conv3 = zext i1 %cmp to i16
441  store i16 %conv3, i16* @globalVal4, align 2
442  ret void
443}
444
445
446define signext i32 @setbc25(i8 signext %a, i8 signext %b) {
447; CHECK-LABEL: setbc25:
448; CHECK:       # %bb.0: # %entry
449; CHECK-NEXT:    cmpw r3, r4
450; CHECK-NEXT:    setbc r3, lt
451; CHECK-NEXT:    blr
452entry:
453  %cmp = icmp slt i8 %a, %b
454  %conv2 = zext i1 %cmp to i32
455  ret i32 %conv2
456}
457
458
459define void @setbc26(i8 signext %a, i8 signext %b) {
460; CHECK-LE-LABEL: setbc26:
461; CHECK-LE:       # %bb.0: # %entry
462; CHECK-LE-NEXT:    cmpw r3, r4
463; CHECK-LE-NEXT:    setbc r3, lt
464; CHECK-LE-NEXT:    pstb r3, globalVal@PCREL(0), 1
465; CHECK-LE-NEXT:    blr
466;
467; CHECK-BE-LABEL: setbc26:
468; CHECK-BE:       # %bb.0: # %entry
469; CHECK-BE-NEXT:    cmpw r3, r4
470; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
471; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
472; CHECK-BE-NEXT:    setbc r3, lt
473; CHECK-BE-NEXT:    stb r3, 0(r4)
474; CHECK-BE-NEXT:    blr
475entry:
476  %cmp = icmp slt i8 %a, %b
477  %conv3 = zext i1 %cmp to i8
478  store i8 %conv3, i8* @globalVal, align 1
479  ret void
480}
481
482
483define void @setbc27(i32 signext %a, i32 signext %b) {
484; CHECK-LE-LABEL: setbc27:
485; CHECK-LE:       # %bb.0: # %entry
486; CHECK-LE-NEXT:    cmpw r3, r4
487; CHECK-LE-NEXT:    setbc r3, lt
488; CHECK-LE-NEXT:    pstw r3, globalVal2@PCREL(0), 1
489; CHECK-LE-NEXT:    blr
490;
491; CHECK-BE-LABEL: setbc27:
492; CHECK-BE:       # %bb.0: # %entry
493; CHECK-BE-NEXT:    cmpw r3, r4
494; CHECK-BE-NEXT:    addis r4, r2, .LC1@toc@ha
495; CHECK-BE-NEXT:    ld r4, .LC1@toc@l(r4)
496; CHECK-BE-NEXT:    setbc r3, lt
497; CHECK-BE-NEXT:    stw r3, 0(r4)
498; CHECK-BE-NEXT:    blr
499entry:
500  %cmp = icmp slt i32 %a, %b
501  %conv = zext i1 %cmp to i32
502  store i32 %conv, i32* @globalVal2, align 4
503  ret void
504}
505
506
507define signext i32 @setbc28(i64 %a, i64 %b) {
508; CHECK-LABEL: setbc28:
509; CHECK:       # %bb.0: # %entry
510; CHECK-NEXT:    cmpd r3, r4
511; CHECK-NEXT:    setbc r3, lt
512; CHECK-NEXT:    blr
513entry:
514  %cmp = icmp slt i64 %a, %b
515  %conv = zext i1 %cmp to i32
516  ret i32 %conv
517}
518
519
520define signext i64 @setbc29(i64 %a, i64 %b) {
521; CHECK-LABEL: setbc29:
522; CHECK:       # %bb.0: # %entry
523; CHECK-NEXT:    cmpd r3, r4
524; CHECK-NEXT:    setbc r3, lt
525; CHECK-NEXT:    blr
526entry:
527  %cmp = icmp slt i64 %a, %b
528  %conv = zext i1 %cmp to i64
529  ret i64 %conv
530}
531
532
533define void @setbc30(i64 %a, i64 %b) {
534; CHECK-LE-LABEL: setbc30:
535; CHECK-LE:       # %bb.0: # %entry
536; CHECK-LE-NEXT:    cmpd r3, r4
537; CHECK-LE-NEXT:    setbc r3, lt
538; CHECK-LE-NEXT:    pstd r3, globalVal3@PCREL(0), 1
539; CHECK-LE-NEXT:    blr
540;
541; CHECK-BE-LABEL: setbc30:
542; CHECK-BE:       # %bb.0: # %entry
543; CHECK-BE-NEXT:    cmpd r3, r4
544; CHECK-BE-NEXT:    addis r4, r2, .LC2@toc@ha
545; CHECK-BE-NEXT:    ld r4, .LC2@toc@l(r4)
546; CHECK-BE-NEXT:    setbc r3, lt
547; CHECK-BE-NEXT:    std r3, 0(r4)
548; CHECK-BE-NEXT:    blr
549entry:
550  %cmp = icmp slt i64 %a, %b
551  %conv1 = zext i1 %cmp to i64
552  store i64 %conv1, i64* @globalVal3, align 8
553  ret void
554}
555
556
557define signext i32 @setbc31(i16 signext %a, i16 signext %b) {
558; CHECK-LABEL: setbc31:
559; CHECK:       # %bb.0: # %entry
560; CHECK-NEXT:    cmpw r3, r4
561; CHECK-NEXT:    setbc r3, lt
562; CHECK-NEXT:    blr
563entry:
564  %cmp = icmp slt i16 %a, %b
565  %conv2 = zext i1 %cmp to i32
566  ret i32 %conv2
567}
568
569
570define void @setbc32(i16 signext %a, i16 signext %b) {
571; CHECK-LE-LABEL: setbc32:
572; CHECK-LE:       # %bb.0: # %entry
573; CHECK-LE-NEXT:    cmpw r3, r4
574; CHECK-LE-NEXT:    setbc r3, lt
575; CHECK-LE-NEXT:    psth r3, globalVal4@PCREL(0), 1
576; CHECK-LE-NEXT:    blr
577;
578; CHECK-BE-LABEL: setbc32:
579; CHECK-BE:       # %bb.0: # %entry
580; CHECK-BE-NEXT:    cmpw r3, r4
581; CHECK-BE-NEXT:    addis r4, r2, .LC3@toc@ha
582; CHECK-BE-NEXT:    ld r4, .LC3@toc@l(r4)
583; CHECK-BE-NEXT:    setbc r3, lt
584; CHECK-BE-NEXT:    sth r3, 0(r4)
585; CHECK-BE-NEXT:    blr
586entry:
587  %cmp = icmp slt i16 %a, %b
588  %conv3 = zext i1 %cmp to i16
589  store i16 %conv3, i16* @globalVal4, align 2
590  ret void
591}
592
593
594define i64 @setbc33(i8 signext %a, i8 signext %b) {
595; CHECK-LABEL: setbc33:
596; CHECK:       # %bb.0: # %entry
597; CHECK-NEXT:    cmpw r3, r4
598; CHECK-NEXT:    setbc r3, eq
599; CHECK-NEXT:    blr
600entry:
601  %cmp = icmp eq i8 %a, %b
602  %conv3 = zext i1 %cmp to i64
603  ret i64 %conv3
604}
605
606
607define void @setbc34(i8 signext %a, i8 signext %b) {
608; CHECK-LE-LABEL: setbc34:
609; CHECK-LE:       # %bb.0: # %entry
610; CHECK-LE-NEXT:    cmpw r3, r4
611; CHECK-LE-NEXT:    setbc r3, eq
612; CHECK-LE-NEXT:    pstb r3, globalVal@PCREL(0), 1
613; CHECK-LE-NEXT:    blr
614;
615; CHECK-BE-LABEL: setbc34:
616; CHECK-BE:       # %bb.0: # %entry
617; CHECK-BE-NEXT:    cmpw r3, r4
618; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
619; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
620; CHECK-BE-NEXT:    setbc r3, eq
621; CHECK-BE-NEXT:    stb r3, 0(r4)
622; CHECK-BE-NEXT:    blr
623entry:
624  %cmp = icmp eq i8 %a, %b
625  %conv3 = zext i1 %cmp to i8
626  store i8 %conv3, i8* @globalVal, align 1
627  ret void
628}
629
630
631define i64 @setbc35(i32 signext %a, i32 signext %b) {
632; CHECK-LABEL: setbc35:
633; CHECK:       # %bb.0: # %entry
634; CHECK-NEXT:    cmpw r3, r4
635; CHECK-NEXT:    setbc r3, eq
636; CHECK-NEXT:    blr
637entry:
638  %cmp = icmp eq i32 %a, %b
639  %conv1 = zext i1 %cmp to i64
640  ret i64 %conv1
641}
642
643
644define void @setbc36(i32 signext %a, i32 signext %b) {
645; CHECK-LE-LABEL: setbc36:
646; CHECK-LE:       # %bb.0: # %entry
647; CHECK-LE-NEXT:    cmpw r3, r4
648; CHECK-LE-NEXT:    setbc r3, eq
649; CHECK-LE-NEXT:    pstw r3, globalVal2@PCREL(0), 1
650; CHECK-LE-NEXT:    blr
651;
652; CHECK-BE-LABEL: setbc36:
653; CHECK-BE:       # %bb.0: # %entry
654; CHECK-BE-NEXT:    cmpw r3, r4
655; CHECK-BE-NEXT:    addis r4, r2, .LC1@toc@ha
656; CHECK-BE-NEXT:    ld r4, .LC1@toc@l(r4)
657; CHECK-BE-NEXT:    setbc r3, eq
658; CHECK-BE-NEXT:    stw r3, 0(r4)
659; CHECK-BE-NEXT:    blr
660entry:
661  %cmp = icmp eq i32 %a, %b
662  %conv = zext i1 %cmp to i32
663  store i32 %conv, i32* @globalVal2, align 4
664  ret void
665}
666
667
668define void @setbc37(i64 %a, i64 %b) {
669; CHECK-LE-LABEL: setbc37:
670; CHECK-LE:       # %bb.0: # %entry
671; CHECK-LE-NEXT:    cmpd r3, r4
672; CHECK-LE-NEXT:    setbc r3, eq
673; CHECK-LE-NEXT:    pstd r3, globalVal3@PCREL(0), 1
674; CHECK-LE-NEXT:    blr
675;
676; CHECK-BE-LABEL: setbc37:
677; CHECK-BE:       # %bb.0: # %entry
678; CHECK-BE-NEXT:    cmpd r3, r4
679; CHECK-BE-NEXT:    addis r4, r2, .LC2@toc@ha
680; CHECK-BE-NEXT:    ld r4, .LC2@toc@l(r4)
681; CHECK-BE-NEXT:    setbc r3, eq
682; CHECK-BE-NEXT:    std r3, 0(r4)
683; CHECK-BE-NEXT:    blr
684entry:
685  %cmp = icmp eq i64 %a, %b
686  %conv1 = zext i1 %cmp to i64
687  store i64 %conv1, i64* @globalVal3, align 8
688  ret void
689}
690
691
692define i64 @setbc38(i16 signext %a, i16 signext %b) {
693; CHECK-LABEL: setbc38:
694; CHECK:       # %bb.0: # %entry
695; CHECK-NEXT:    cmpw r3, r4
696; CHECK-NEXT:    setbc r3, eq
697; CHECK-NEXT:    blr
698entry:
699  %cmp = icmp eq i16 %a, %b
700  %conv3 = zext i1 %cmp to i64
701  ret i64 %conv3
702}
703
704
705define void @setbc39(i16 signext %a, i16 signext %b) {
706; CHECK-LE-LABEL: setbc39:
707; CHECK-LE:       # %bb.0: # %entry
708; CHECK-LE-NEXT:    cmpw r3, r4
709; CHECK-LE-NEXT:    setbc r3, eq
710; CHECK-LE-NEXT:    psth r3, globalVal4@PCREL(0), 1
711; CHECK-LE-NEXT:    blr
712;
713; CHECK-BE-LABEL: setbc39:
714; CHECK-BE:       # %bb.0: # %entry
715; CHECK-BE-NEXT:    cmpw r3, r4
716; CHECK-BE-NEXT:    addis r4, r2, .LC3@toc@ha
717; CHECK-BE-NEXT:    ld r4, .LC3@toc@l(r4)
718; CHECK-BE-NEXT:    setbc r3, eq
719; CHECK-BE-NEXT:    sth r3, 0(r4)
720; CHECK-BE-NEXT:    blr
721entry:
722  %cmp = icmp eq i16 %a, %b
723  %conv3 = zext i1 %cmp to i16
724  store i16 %conv3, i16* @globalVal4, align 2
725  ret void
726}
727
728
729define i64 @setbc40(i8 zeroext %a, i8 zeroext %b) {
730; CHECK-LABEL: setbc40:
731; CHECK:       # %bb.0: # %entry
732; CHECK-NEXT:    cmpw r3, r4
733; CHECK-NEXT:    setbc r3, eq
734; CHECK-NEXT:    blr
735entry:
736  %cmp = icmp eq i8 %a, %b
737  %conv3 = zext i1 %cmp to i64
738  ret i64 %conv3
739}
740
741
742define void @setbc41(i8 zeroext %a, i8 zeroext %b) {
743; CHECK-LE-LABEL: setbc41:
744; CHECK-LE:       # %bb.0: # %entry
745; CHECK-LE-NEXT:    cmpw r3, r4
746; CHECK-LE-NEXT:    setbc r3, eq
747; CHECK-LE-NEXT:    pstb r3, globalVal@PCREL(0), 1
748; CHECK-LE-NEXT:    blr
749;
750; CHECK-BE-LABEL: setbc41:
751; CHECK-BE:       # %bb.0: # %entry
752; CHECK-BE-NEXT:    cmpw r3, r4
753; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
754; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
755; CHECK-BE-NEXT:    setbc r3, eq
756; CHECK-BE-NEXT:    stb r3, 0(r4)
757; CHECK-BE-NEXT:    blr
758entry:
759  %cmp = icmp eq i8 %a, %b
760  %conv3 = zext i1 %cmp to i8
761  store i8 %conv3, i8* @globalVal, align 1
762  ret void
763}
764
765
766define i64 @setbc42(i32 zeroext %a, i32 zeroext %b) {
767; CHECK-LABEL: setbc42:
768; CHECK:       # %bb.0: # %entry
769; CHECK-NEXT:    cmpw r3, r4
770; CHECK-NEXT:    setbc r3, eq
771; CHECK-NEXT:    blr
772entry:
773  %cmp = icmp eq i32 %a, %b
774  %conv1 = zext i1 %cmp to i64
775  ret i64 %conv1
776}
777
778
779define void @setbc43(i32 zeroext %a, i32 zeroext %b) {
780; CHECK-LE-LABEL: setbc43:
781; CHECK-LE:       # %bb.0: # %entry
782; CHECK-LE-NEXT:    cmpw r3, r4
783; CHECK-LE-NEXT:    setbc r3, eq
784; CHECK-LE-NEXT:    pstw r3, globalVal2@PCREL(0), 1
785; CHECK-LE-NEXT:    blr
786;
787; CHECK-BE-LABEL: setbc43:
788; CHECK-BE:       # %bb.0: # %entry
789; CHECK-BE-NEXT:    cmpw r3, r4
790; CHECK-BE-NEXT:    addis r4, r2, .LC1@toc@ha
791; CHECK-BE-NEXT:    ld r4, .LC1@toc@l(r4)
792; CHECK-BE-NEXT:    setbc r3, eq
793; CHECK-BE-NEXT:    stw r3, 0(r4)
794; CHECK-BE-NEXT:    blr
795entry:
796  %cmp = icmp eq i32 %a, %b
797  %conv = zext i1 %cmp to i32
798  store i32 %conv, i32* @globalVal2, align 4
799  ret void
800}
801
802
803define i64 @setbc44(i64 %a, i64 %b) {
804; CHECK-LABEL: setbc44:
805; CHECK:       # %bb.0: # %entry
806; CHECK-NEXT:    cmpd r3, r4
807; CHECK-NEXT:    setbc r3, eq
808; CHECK-NEXT:    blr
809entry:
810  %cmp = icmp eq i64 %a, %b
811  %conv1 = zext i1 %cmp to i64
812  ret i64 %conv1
813}
814
815
816define void @setbc45(i64 %a, i64 %b) {
817; CHECK-LE-LABEL: setbc45:
818; CHECK-LE:       # %bb.0: # %entry
819; CHECK-LE-NEXT:    cmpd r3, r4
820; CHECK-LE-NEXT:    setbc r3, eq
821; CHECK-LE-NEXT:    pstd r3, globalVal3@PCREL(0), 1
822; CHECK-LE-NEXT:    blr
823;
824; CHECK-BE-LABEL: setbc45:
825; CHECK-BE:       # %bb.0: # %entry
826; CHECK-BE-NEXT:    cmpd r3, r4
827; CHECK-BE-NEXT:    addis r4, r2, .LC2@toc@ha
828; CHECK-BE-NEXT:    ld r4, .LC2@toc@l(r4)
829; CHECK-BE-NEXT:    setbc r3, eq
830; CHECK-BE-NEXT:    std r3, 0(r4)
831; CHECK-BE-NEXT:    blr
832entry:
833  %cmp = icmp eq i64 %a, %b
834  %conv1 = zext i1 %cmp to i64
835  store i64 %conv1, i64* @globalVal3, align 8
836  ret void
837}
838
839
840define i64 @setbc46(i16 zeroext %a, i16 zeroext %b) {
841; CHECK-LABEL: setbc46:
842; CHECK:       # %bb.0: # %entry
843; CHECK-NEXT:    cmpw r3, r4
844; CHECK-NEXT:    setbc r3, eq
845; CHECK-NEXT:    blr
846entry:
847  %cmp = icmp eq i16 %a, %b
848  %conv3 = zext i1 %cmp to i64
849  ret i64 %conv3
850}
851
852
853define void @setbc47(i16 zeroext %a, i16 zeroext %b) {
854; CHECK-LE-LABEL: setbc47:
855; CHECK-LE:       # %bb.0: # %entry
856; CHECK-LE-NEXT:    cmpw r3, r4
857; CHECK-LE-NEXT:    setbc r3, eq
858; CHECK-LE-NEXT:    psth r3, globalVal4@PCREL(0), 1
859; CHECK-LE-NEXT:    blr
860;
861; CHECK-BE-LABEL: setbc47:
862; CHECK-BE:       # %bb.0: # %entry
863; CHECK-BE-NEXT:    cmpw r3, r4
864; CHECK-BE-NEXT:    addis r4, r2, .LC3@toc@ha
865; CHECK-BE-NEXT:    ld r4, .LC3@toc@l(r4)
866; CHECK-BE-NEXT:    setbc r3, eq
867; CHECK-BE-NEXT:    sth r3, 0(r4)
868; CHECK-BE-NEXT:    blr
869entry:
870  %cmp = icmp eq i16 %a, %b
871  %conv3 = zext i1 %cmp to i16
872  store i16 %conv3, i16* @globalVal4, align 2
873  ret void
874}
875
876
877define i64 @setbc48(i64 %a, i64 %b) {
878; CHECK-LABEL: setbc48:
879; CHECK:       # %bb.0: # %entry
880; CHECK-NEXT:    cmpd r3, r4
881; CHECK-NEXT:    setbc r3, gt
882; CHECK-NEXT:    blr
883entry:
884  %cmp = icmp sgt i64 %a, %b
885  %conv1 = zext i1 %cmp to i64
886  ret i64 %conv1
887}
888
889
890define void @setbc49(i64 %a, i64 %b) {
891; CHECK-LE-LABEL: setbc49:
892; CHECK-LE:       # %bb.0: # %entry
893; CHECK-LE-NEXT:    cmpd r3, r4
894; CHECK-LE-NEXT:    setbc r3, gt
895; CHECK-LE-NEXT:    pstd r3, globalVal3@PCREL(0), 1
896; CHECK-LE-NEXT:    blr
897;
898; CHECK-BE-LABEL: setbc49:
899; CHECK-BE:       # %bb.0: # %entry
900; CHECK-BE-NEXT:    cmpd r3, r4
901; CHECK-BE-NEXT:    addis r4, r2, .LC2@toc@ha
902; CHECK-BE-NEXT:    ld r4, .LC2@toc@l(r4)
903; CHECK-BE-NEXT:    setbc r3, gt
904; CHECK-BE-NEXT:    std r3, 0(r4)
905; CHECK-BE-NEXT:    blr
906entry:
907  %cmp = icmp sgt i64 %a, %b
908  %conv1 = zext i1 %cmp to i64
909  store i64 %conv1, i64* @globalVal3, align 8
910  ret void
911}
912
913
914define i64 @setbc50(i64 %a, i64 %b) {
915; CHECK-LABEL: setbc50:
916; CHECK:       # %bb.0: # %entry
917; CHECK-NEXT:    cmpd r3, r4
918; CHECK-NEXT:    setbc r3, lt
919; CHECK-NEXT:    blr
920entry:
921  %cmp = icmp slt i64 %a, %b
922  %conv1 = zext i1 %cmp to i64
923  ret i64 %conv1
924}
925
926
927define void @setnbc51(i64 %a, i64 %b) {
928; CHECK-LE-LABEL: setnbc51:
929; CHECK-LE:       # %bb.0: # %entry
930; CHECK-LE-NEXT:    cmpd r3, r4
931; CHECK-LE-NEXT:    setbc r3, lt
932; CHECK-LE-NEXT:    pstd r3, globalVal3@PCREL(0), 1
933; CHECK-LE-NEXT:    blr
934;
935; CHECK-BE-LABEL: setnbc51:
936; CHECK-BE:       # %bb.0: # %entry
937; CHECK-BE-NEXT:    cmpd r3, r4
938; CHECK-BE-NEXT:    addis r4, r2, .LC2@toc@ha
939; CHECK-BE-NEXT:    ld r4, .LC2@toc@l(r4)
940; CHECK-BE-NEXT:    setbc r3, lt
941; CHECK-BE-NEXT:    std r3, 0(r4)
942; CHECK-BE-NEXT:    blr
943entry:
944  %cmp = icmp slt i64 %a, %b
945  %conv1 = zext i1 %cmp to i64
946  store i64 %conv1, i64* @globalVal3, align 8
947  ret void
948}
949