1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ 3; RUN: -ppc-asm-full-reg-names -mcpu=pwr10 < %s | FileCheck %s \ 4; RUN: --check-prefixes=CHECK,CHECK-LE 5; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ 6; RUN: -ppc-asm-full-reg-names -mcpu=pwr10 < %s | FileCheck %s \ 7; RUN: --check-prefixes=CHECK,CHECK-BE 8 9; This file does not contain many test cases involving comparisons and logical 10; comparisons (cmplwi, cmpldi). This is because alternative code is generated 11; when there is a compare (logical or not), followed by a sign or zero extend. 12; This codegen will be re-evaluated at a later time on whether or not it should 13; be emitted on P10. 14 15@globalVal = common local_unnamed_addr global i8 0, align 1 16@globalVal2 = common local_unnamed_addr global i32 0, align 4 17@globalVal3 = common local_unnamed_addr global i64 0, align 8 18@globalVal4 = common local_unnamed_addr global i16 0, align 2 19 20define signext i32 @setbcr1(i8 %a) { 21; CHECK-LABEL: setbcr1: 22; CHECK: # %bb.0: # %entry 23; CHECK-NEXT: clrlwi r3, r3, 24 24; CHECK-NEXT: cmpwi r3, 1 25; CHECK-NEXT: setbcr r3, eq 26; CHECK-NEXT: blr 27entry: 28 %cmp = icmp ne i8 %a, 1 29 %conv = zext i1 %cmp to i32 30 ret i32 %conv 31} 32 33define signext i32 @setbcr2(i32 %a) { 34; CHECK-LABEL: setbcr2: 35; CHECK: # %bb.0: # %entry 36; CHECK-NEXT: cmpwi r3, 1 37; CHECK-NEXT: setbcr r3, eq 38; CHECK-NEXT: blr 39entry: 40 %cmp = icmp ne i32 %a, 1 41 %conv = zext i1 %cmp to i32 42 ret i32 %conv 43} 44 45define signext i32 @setbcr3(i64 %a) { 46; CHECK-LABEL: setbcr3: 47; CHECK: # %bb.0: # %entry 48; CHECK-NEXT: cmpdi r3, 1 49; CHECK-NEXT: setbcr r3, eq 50; CHECK-NEXT: blr 51entry: 52 %cmp = icmp ne i64 %a, 1 53 %conv = zext i1 %cmp to i32 54 ret i32 %conv 55} 56 57define signext i32 @setbcr4(i16 %a) { 58; CHECK-LABEL: setbcr4: 59; CHECK: # %bb.0: # %entry 60; CHECK-NEXT: clrlwi r3, r3, 16 61; CHECK-NEXT: cmpwi r3, 1 62; CHECK-NEXT: setbcr r3, eq 63; CHECK-NEXT: blr 64entry: 65 %cmp = icmp ne i16 %a, 1 66 %conv = zext i1 %cmp to i32 67 ret i32 %conv 68} 69 70define signext i64 @setbcr5(i8 %a) { 71; CHECK-LABEL: setbcr5: 72; CHECK: # %bb.0: # %entry 73; CHECK-NEXT: clrlwi r3, r3, 24 74; CHECK-NEXT: cmpwi r3, 1 75; CHECK-NEXT: setbcr r3, eq 76; CHECK-NEXT: blr 77entry: 78 %cmp = icmp ne i8 %a, 1 79 %conv = zext i1 %cmp to i64 80 ret i64 %conv 81} 82 83define signext i64 @setbcr6(i32 %a) { 84; CHECK-LABEL: setbcr6: 85; CHECK: # %bb.0: # %entry 86; CHECK-NEXT: cmpwi r3, 1 87; CHECK-NEXT: setbcr r3, eq 88; CHECK-NEXT: blr 89entry: 90 %cmp = icmp ne i32 %a, 1 91 %conv = zext i1 %cmp to i64 92 ret i64 %conv 93} 94 95define signext i64 @setbcr7(i64 %a) { 96; CHECK-LABEL: setbcr7: 97; CHECK: # %bb.0: # %entry 98; CHECK-NEXT: cmpdi r3, 1 99; CHECK-NEXT: setbcr r3, eq 100; CHECK-NEXT: blr 101entry: 102 %cmp = icmp ne i64 %a, 1 103 %conv = zext i1 %cmp to i64 104 ret i64 %conv 105} 106 107define signext i64 @setbcr8(i16 %a) { 108; CHECK-LABEL: setbcr8: 109; CHECK: # %bb.0: # %entry 110; CHECK-NEXT: clrlwi r3, r3, 16 111; CHECK-NEXT: cmpwi r3, 1 112; CHECK-NEXT: setbcr r3, eq 113; CHECK-NEXT: blr 114entry: 115 %cmp = icmp ne i16 %a, 1 116 %conv = zext i1 %cmp to i64 117 ret i64 %conv 118} 119 120define void @setbcr9(i8 %a) { 121; CHECK-LE-LABEL: setbcr9: 122; CHECK-LE: # %bb.0: # %entry 123; CHECK-LE-NEXT: clrlwi r3, r3, 24 124; CHECK-LE-NEXT: cmpwi r3, 1 125; CHECK-LE-NEXT: setbcr r3, eq 126; CHECK-LE-NEXT: pstb r3, globalVal@PCREL(0), 1 127; CHECK-LE-NEXT: blr 128; 129; CHECK-BE-LABEL: setbcr9: 130; CHECK-BE: # %bb.0: # %entry 131; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha 132; CHECK-BE-NEXT: clrlwi r3, r3, 24 133; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) 134; CHECK-BE-NEXT: cmpwi r3, 1 135; CHECK-BE-NEXT: setbcr r3, eq 136; CHECK-BE-NEXT: stb r3, 0(r4) 137; CHECK-BE-NEXT: blr 138entry: 139 %cmp = icmp ne i8 %a, 1 140 %conv1 = zext i1 %cmp to i8 141 store i8 %conv1, i8* @globalVal, align 1 142 ret void 143} 144 145define void @setbcr10(i32 %a) { 146; CHECK-LE-LABEL: setbcr10: 147; CHECK-LE: # %bb.0: # %entry 148; CHECK-LE-NEXT: cmpwi r3, 1 149; CHECK-LE-NEXT: setbcr r3, eq 150; CHECK-LE-NEXT: pstw r3, globalVal2@PCREL(0), 1 151; CHECK-LE-NEXT: blr 152; 153; CHECK-BE-LABEL: setbcr10: 154; CHECK-BE: # %bb.0: # %entry 155; CHECK-BE-NEXT: addis r4, r2, .LC1@toc@ha 156; CHECK-BE-NEXT: cmpwi r3, 1 157; CHECK-BE-NEXT: ld r4, .LC1@toc@l(r4) 158; CHECK-BE-NEXT: setbcr r3, eq 159; CHECK-BE-NEXT: stw r3, 0(r4) 160; CHECK-BE-NEXT: blr 161entry: 162 %cmp = icmp ne i32 %a, 1 163 %conv1 = zext i1 %cmp to i32 164 store i32 %conv1, i32* @globalVal2, align 4 165 ret void 166} 167 168define void @setbcr11(i64 %a) { 169; CHECK-LE-LABEL: setbcr11: 170; CHECK-LE: # %bb.0: # %entry 171; CHECK-LE-NEXT: cmpdi r3, 1 172; CHECK-LE-NEXT: setbcr r3, eq 173; CHECK-LE-NEXT: pstd r3, globalVal3@PCREL(0), 1 174; CHECK-LE-NEXT: blr 175; 176; CHECK-BE-LABEL: setbcr11: 177; CHECK-BE: # %bb.0: # %entry 178; CHECK-BE-NEXT: addis r4, r2, .LC2@toc@ha 179; CHECK-BE-NEXT: cmpdi r3, 1 180; CHECK-BE-NEXT: ld r4, .LC2@toc@l(r4) 181; CHECK-BE-NEXT: setbcr r3, eq 182; CHECK-BE-NEXT: std r3, 0(r4) 183; CHECK-BE-NEXT: blr 184entry: 185 %cmp = icmp ne i64 %a, 1 186 %conv1 = zext i1 %cmp to i64 187 store i64 %conv1, i64* @globalVal3, align 8 188 ret void 189} 190 191define void @setbcr12(i16 %a) { 192; CHECK-LE-LABEL: setbcr12: 193; CHECK-LE: # %bb.0: # %entry 194; CHECK-LE-NEXT: clrlwi r3, r3, 16 195; CHECK-LE-NEXT: cmpwi r3, 1 196; CHECK-LE-NEXT: setbcr r3, eq 197; CHECK-LE-NEXT: psth r3, globalVal4@PCREL(0), 1 198; CHECK-LE-NEXT: blr 199; 200; CHECK-BE-LABEL: setbcr12: 201; CHECK-BE: # %bb.0: # %entry 202; CHECK-BE-NEXT: addis r4, r2, .LC3@toc@ha 203; CHECK-BE-NEXT: clrlwi r3, r3, 16 204; CHECK-BE-NEXT: ld r4, .LC3@toc@l(r4) 205; CHECK-BE-NEXT: cmpwi r3, 1 206; CHECK-BE-NEXT: setbcr r3, eq 207; CHECK-BE-NEXT: sth r3, 0(r4) 208; CHECK-BE-NEXT: blr 209entry: 210 %cmp = icmp ne i16 %a, 1 211 %conv1 = zext i1 %cmp to i16 212 store i16 %conv1, i16* @globalVal4, align 2 213 ret void 214} 215 216