1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ 3; RUN: -ppc-asm-full-reg-names -mcpu=pwr10 < %s | FileCheck %s \ 4; RUN: --check-prefixes=CHECK,CHECK-LE 5; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ 6; RUN: -ppc-asm-full-reg-names -mcpu=pwr10 < %s | FileCheck %s \ 7; RUN: --check-prefixes=CHECK,CHECK-BE 8 9; This file does not contain many test cases involving comparisons and logical 10; comparisons (cmplwi, cmpldi). This is because alternative code is generated 11; when there is a compare (logical or not), followed by a sign or zero extend. 12; This codegen will be re-evaluated at a later time on whether or not it should 13; be emitted on P10. 14 15@globalVal = common local_unnamed_addr global i8 0, align 1 16@globalVal2 = common local_unnamed_addr global i32 0, align 4 17@globalVal3 = common local_unnamed_addr global i64 0, align 8 18@globalVal4 = common local_unnamed_addr global i16 0, align 2 19 20define signext i32 @setnbc1(i32 signext %a, i32 signext %b) { 21; CHECK-LABEL: setnbc1: 22; CHECK: # %bb.0: # %entry 23; CHECK-NEXT: cmpw r3, r4 24; CHECK-NEXT: setnbc r3, lt 25; CHECK-NEXT: blr 26entry: 27 %cmp = icmp slt i32 %a, %b 28 %conv = sext i1 %cmp to i32 29 ret i32 %conv 30} 31 32define signext i32 @setnbc2(i32 signext %a, i32 signext %b) { 33; CHECK-LABEL: setnbc2: 34; CHECK: # %bb.0: # %entry 35; CHECK-NEXT: cmpw r3, r4 36; CHECK-NEXT: setnbc r3, eq 37; CHECK-NEXT: blr 38entry: 39 %cmp = icmp eq i32 %a, %b 40 %conv = sext i1 %cmp to i32 41 ret i32 %conv 42} 43 44define signext i32 @setnbc3(i32 signext %a, i32 signext %b) { 45; CHECK-LABEL: setnbc3: 46; CHECK: # %bb.0: # %entry 47; CHECK-NEXT: cmpw r3, r4 48; CHECK-NEXT: setnbc r3, gt 49; CHECK-NEXT: blr 50entry: 51 %cmp = icmp sgt i32 %a, %b 52 %conv = sext i1 %cmp to i32 53 ret i32 %conv 54} 55 56define signext i32 @setnbc4(i8 signext %a, i8 signext %b) { 57; CHECK-LABEL: setnbc4: 58; CHECK: # %bb.0: # %entry 59; CHECK-NEXT: cmpw r3, r4 60; CHECK-NEXT: setnbc r3, eq 61; CHECK-NEXT: blr 62entry: 63 %cmp = icmp eq i8 %a, %b 64 %conv = sext i1 %cmp to i32 65 ret i32 %conv 66} 67 68; function attrs: norecurse nounwind 69define void @setnbc5(i8 signext %a, i8 signext %b) { 70; CHECK-LE-LABEL: setnbc5: 71; CHECK-LE: # %bb.0: # %entry 72; CHECK-LE-NEXT: cmpw r3, r4 73; CHECK-LE-NEXT: setnbc r3, eq 74; CHECK-LE-NEXT: pstb r3, globalVal@PCREL(0), 1 75; CHECK-LE-NEXT: blr 76; 77; CHECK-BE-LABEL: setnbc5: 78; CHECK-BE: # %bb.0: # %entry 79; CHECK-BE-NEXT: cmpw r3, r4 80; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha 81; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) 82; CHECK-BE-NEXT: setnbc r3, eq 83; CHECK-BE-NEXT: stb r3, 0(r4) 84; CHECK-BE-NEXT: blr 85entry: 86 %cmp = icmp eq i8 %a, %b 87 %conv3 = sext i1 %cmp to i8 88 store i8 %conv3, i8* @globalVal, align 1 89 ret void 90} 91 92define void @setnbc6(i32 signext %a, i32 signext %b) { 93; CHECK-LE-LABEL: setnbc6: 94; CHECK-LE: # %bb.0: # %entry 95; CHECK-LE-NEXT: cmpw r3, r4 96; CHECK-LE-NEXT: setnbc r3, eq 97; CHECK-LE-NEXT: pstw r3, globalVal2@PCREL(0), 1 98; CHECK-LE-NEXT: blr 99; 100; CHECK-BE-LABEL: setnbc6: 101; CHECK-BE: # %bb.0: # %entry 102; CHECK-BE-NEXT: cmpw r3, r4 103; CHECK-BE-NEXT: addis r4, r2, .LC1@toc@ha 104; CHECK-BE-NEXT: ld r4, .LC1@toc@l(r4) 105; CHECK-BE-NEXT: setnbc r3, eq 106; CHECK-BE-NEXT: stw r3, 0(r4) 107; CHECK-BE-NEXT: blr 108entry: 109 %cmp = icmp eq i32 %a, %b 110 %conv = sext i1 %cmp to i32 111 store i32 %conv, i32* @globalVal2, align 4 112 ret void 113} 114 115define signext i32 @setnbc7(i64 %a, i64 %b) { 116; CHECK-LABEL: setnbc7: 117; CHECK: # %bb.0: # %entry 118; CHECK-NEXT: cmpd r3, r4 119; CHECK-NEXT: setnbc r3, eq 120; CHECK-NEXT: blr 121entry: 122 %cmp = icmp eq i64 %a, %b 123 %conv = sext i1 %cmp to i32 124 ret i32 %conv 125} 126 127define signext i64 @setnbc8(i64 %a, i64 %b) { 128; CHECK-LABEL: setnbc8: 129; CHECK: # %bb.0: # %entry 130; CHECK-NEXT: cmpd r3, r4 131; CHECK-NEXT: setnbc r3, eq 132; CHECK-NEXT: blr 133entry: 134 %cmp = icmp eq i64 %a, %b 135 %conv = sext i1 %cmp to i64 136 ret i64 %conv 137} 138 139define void @setnbc9(i64 %a, i64 %b) { 140; CHECK-LE-LABEL: setnbc9: 141; CHECK-LE: # %bb.0: # %entry 142; CHECK-LE-NEXT: cmpd r3, r4 143; CHECK-LE-NEXT: setnbc r3, eq 144; CHECK-LE-NEXT: pstd r3, globalVal3@PCREL(0), 1 145; CHECK-LE-NEXT: blr 146; 147; CHECK-BE-LABEL: setnbc9: 148; CHECK-BE: # %bb.0: # %entry 149; CHECK-BE-NEXT: cmpd r3, r4 150; CHECK-BE-NEXT: addis r4, r2, .LC2@toc@ha 151; CHECK-BE-NEXT: ld r4, .LC2@toc@l(r4) 152; CHECK-BE-NEXT: setnbc r3, eq 153; CHECK-BE-NEXT: std r3, 0(r4) 154; CHECK-BE-NEXT: blr 155entry: 156 %cmp = icmp eq i64 %a, %b 157 %conv1 = sext i1 %cmp to i64 158 store i64 %conv1, i64* @globalVal3, align 8 159 ret void 160} 161 162define signext i32 @setnbc10(i16 signext %a, i16 signext %b) { 163; CHECK-LABEL: setnbc10: 164; CHECK: # %bb.0: # %entry 165; CHECK-NEXT: cmpw r3, r4 166; CHECK-NEXT: setnbc r3, eq 167; CHECK-NEXT: blr 168entry: 169 %cmp = icmp eq i16 %a, %b 170 %conv = sext i1 %cmp to i32 171 ret i32 %conv 172} 173 174define void @setnbc11(i16 signext %a, i16 signext %b) { 175; CHECK-LE-LABEL: setnbc11: 176; CHECK-LE: # %bb.0: # %entry 177; CHECK-LE-NEXT: cmpw r3, r4 178; CHECK-LE-NEXT: setnbc r3, eq 179; CHECK-LE-NEXT: psth r3, globalVal4@PCREL(0), 1 180; CHECK-LE-NEXT: blr 181; 182; CHECK-BE-LABEL: setnbc11: 183; CHECK-BE: # %bb.0: # %entry 184; CHECK-BE-NEXT: cmpw r3, r4 185; CHECK-BE-NEXT: addis r4, r2, .LC3@toc@ha 186; CHECK-BE-NEXT: ld r4, .LC3@toc@l(r4) 187; CHECK-BE-NEXT: setnbc r3, eq 188; CHECK-BE-NEXT: sth r3, 0(r4) 189; CHECK-BE-NEXT: blr 190entry: 191 %cmp = icmp eq i16 %a, %b 192 %conv3 = sext i1 %cmp to i16 193 store i16 %conv3, i16* @globalVal4, align 2 194 ret void 195} 196 197define signext i32 @setnbc12(i8 zeroext %a, i8 zeroext %b) { 198; CHECK-LABEL: setnbc12: 199; CHECK: # %bb.0: # %entry 200; CHECK-NEXT: cmpw r3, r4 201; CHECK-NEXT: setnbc r3, eq 202; CHECK-NEXT: blr 203entry: 204 %cmp = icmp eq i8 %a, %b 205 %conv = sext i1 %cmp to i32 206 ret i32 %conv 207} 208 209define void @setnbc13(i8 zeroext %a, i8 zeroext %b) { 210; CHECK-LE-LABEL: setnbc13: 211; CHECK-LE: # %bb.0: # %entry 212; CHECK-LE-NEXT: cmpw r3, r4 213; CHECK-LE-NEXT: setnbc r3, eq 214; CHECK-LE-NEXT: pstb r3, globalVal@PCREL(0), 1 215; CHECK-LE-NEXT: blr 216; 217; CHECK-BE-LABEL: setnbc13: 218; CHECK-BE: # %bb.0: # %entry 219; CHECK-BE-NEXT: cmpw r3, r4 220; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha 221; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) 222; CHECK-BE-NEXT: setnbc r3, eq 223; CHECK-BE-NEXT: stb r3, 0(r4) 224; CHECK-BE-NEXT: blr 225entry: 226 %cmp = icmp eq i8 %a, %b 227 %conv3 = sext i1 %cmp to i8 228 store i8 %conv3, i8* @globalVal, align 1 229 ret void 230} 231 232define signext i32 @setnbc14(i32 zeroext %a, i32 zeroext %b) { 233; CHECK-LABEL: setnbc14: 234; CHECK: # %bb.0: # %entry 235; CHECK-NEXT: cmpw r3, r4 236; CHECK-NEXT: setnbc r3, eq 237; CHECK-NEXT: blr 238entry: 239 %cmp = icmp eq i32 %a, %b 240 %conv = sext i1 %cmp to i32 241 ret i32 %conv 242} 243 244define void @setnbc15(i32 zeroext %a, i32 zeroext %b) { 245; CHECK-LE-LABEL: setnbc15: 246; CHECK-LE: # %bb.0: # %entry 247; CHECK-LE-NEXT: cmpw r3, r4 248; CHECK-LE-NEXT: setnbc r3, eq 249; CHECK-LE-NEXT: pstw r3, globalVal2@PCREL(0), 1 250; CHECK-LE-NEXT: blr 251; 252; CHECK-BE-LABEL: setnbc15: 253; CHECK-BE: # %bb.0: # %entry 254; CHECK-BE-NEXT: cmpw r3, r4 255; CHECK-BE-NEXT: addis r4, r2, .LC1@toc@ha 256; CHECK-BE-NEXT: ld r4, .LC1@toc@l(r4) 257; CHECK-BE-NEXT: setnbc r3, eq 258; CHECK-BE-NEXT: stw r3, 0(r4) 259; CHECK-BE-NEXT: blr 260entry: 261 %cmp = icmp eq i32 %a, %b 262 %conv = sext i1 %cmp to i32 263 store i32 %conv, i32* @globalVal2, align 4 264 ret void 265} 266 267define signext i32 @setnbc16(i16 zeroext %a, i16 zeroext %b) { 268; CHECK-LABEL: setnbc16: 269; CHECK: # %bb.0: # %entry 270; CHECK-NEXT: cmpw r3, r4 271; CHECK-NEXT: setnbc r3, eq 272; CHECK-NEXT: blr 273entry: 274 %cmp = icmp eq i16 %a, %b 275 %conv = sext i1 %cmp to i32 276 ret i32 %conv 277} 278 279define void @setnbc17(i16 zeroext %a, i16 zeroext %b) { 280; CHECK-LE-LABEL: setnbc17: 281; CHECK-LE: # %bb.0: # %entry 282; CHECK-LE-NEXT: cmpw r3, r4 283; CHECK-LE-NEXT: setnbc r3, eq 284; CHECK-LE-NEXT: psth r3, globalVal4@PCREL(0), 1 285; CHECK-LE-NEXT: blr 286; 287; CHECK-BE-LABEL: setnbc17: 288; CHECK-BE: # %bb.0: # %entry 289; CHECK-BE-NEXT: cmpw r3, r4 290; CHECK-BE-NEXT: addis r4, r2, .LC3@toc@ha 291; CHECK-BE-NEXT: ld r4, .LC3@toc@l(r4) 292; CHECK-BE-NEXT: setnbc r3, eq 293; CHECK-BE-NEXT: sth r3, 0(r4) 294; CHECK-BE-NEXT: blr 295entry: 296 %cmp = icmp eq i16 %a, %b 297 %conv3 = sext i1 %cmp to i16 298 store i16 %conv3, i16* @globalVal4, align 2 299 ret void 300} 301 302define signext i32 @setnbc18(i8 signext %a, i8 signext %b) { 303; CHECK-LABEL: setnbc18: 304; CHECK: # %bb.0: # %entry 305; CHECK-NEXT: cmpw r3, r4 306; CHECK-NEXT: setnbc r3, gt 307; CHECK-NEXT: blr 308entry: 309 %cmp = icmp sgt i8 %a, %b 310 %sub = sext i1 %cmp to i32 311 ret i32 %sub 312} 313 314define void @setnbc19(i8 signext %a, i8 signext %b) { 315; CHECK-LE-LABEL: setnbc19: 316; CHECK-LE: # %bb.0: # %entry 317; CHECK-LE-NEXT: cmpw r3, r4 318; CHECK-LE-NEXT: setnbc r3, gt 319; CHECK-LE-NEXT: pstb r3, globalVal@PCREL(0), 1 320; CHECK-LE-NEXT: blr 321; 322; CHECK-BE-LABEL: setnbc19: 323; CHECK-BE: # %bb.0: # %entry 324; CHECK-BE-NEXT: cmpw r3, r4 325; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha 326; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) 327; CHECK-BE-NEXT: setnbc r3, gt 328; CHECK-BE-NEXT: stb r3, 0(r4) 329; CHECK-BE-NEXT: blr 330entry: 331 %cmp = icmp sgt i8 %a, %b 332 %conv3 = sext i1 %cmp to i8 333 store i8 %conv3, i8* @globalVal, align 1 334 ret void 335} 336 337define void @setnbc20(i32 signext %a, i32 signext %b) { 338; CHECK-LE-LABEL: setnbc20: 339; CHECK-LE: # %bb.0: # %entry 340; CHECK-LE-NEXT: cmpw r3, r4 341; CHECK-LE-NEXT: setnbc r3, gt 342; CHECK-LE-NEXT: pstw r3, globalVal2@PCREL(0), 1 343; CHECK-LE-NEXT: blr 344; 345; CHECK-BE-LABEL: setnbc20: 346; CHECK-BE: # %bb.0: # %entry 347; CHECK-BE-NEXT: cmpw r3, r4 348; CHECK-BE-NEXT: addis r4, r2, .LC1@toc@ha 349; CHECK-BE-NEXT: ld r4, .LC1@toc@l(r4) 350; CHECK-BE-NEXT: setnbc r3, gt 351; CHECK-BE-NEXT: stw r3, 0(r4) 352; CHECK-BE-NEXT: blr 353entry: 354 %cmp = icmp sgt i32 %a, %b 355 %sub = sext i1 %cmp to i32 356 store i32 %sub, i32* @globalVal2, align 4 357 ret void 358} 359 360define signext i32 @setnbc21(i64 %a, i64 %b) { 361; CHECK-LABEL: setnbc21: 362; CHECK: # %bb.0: # %entry 363; CHECK-NEXT: cmpd r3, r4 364; CHECK-NEXT: setnbc r3, gt 365; CHECK-NEXT: blr 366entry: 367 %cmp = icmp sgt i64 %a, %b 368 %sub = sext i1 %cmp to i32 369 ret i32 %sub 370} 371 372define void @setnbc22(i64 %a, i64 %b) { 373; CHECK-LE-LABEL: setnbc22: 374; CHECK-LE: # %bb.0: # %entry 375; CHECK-LE-NEXT: cmpd r3, r4 376; CHECK-LE-NEXT: setnbc r3, gt 377; CHECK-LE-NEXT: pstd r3, globalVal3@PCREL(0), 1 378; CHECK-LE-NEXT: blr 379; 380; CHECK-BE-LABEL: setnbc22: 381; CHECK-BE: # %bb.0: # %entry 382; CHECK-BE-NEXT: cmpd r3, r4 383; CHECK-BE-NEXT: addis r4, r2, .LC2@toc@ha 384; CHECK-BE-NEXT: ld r4, .LC2@toc@l(r4) 385; CHECK-BE-NEXT: setnbc r3, gt 386; CHECK-BE-NEXT: std r3, 0(r4) 387; CHECK-BE-NEXT: blr 388entry: 389 %cmp = icmp sgt i64 %a, %b 390 %conv1 = sext i1 %cmp to i64 391 store i64 %conv1, i64* @globalVal3, align 8 392 ret void 393} 394 395define signext i32 @setnbc23(i16 signext %a, i16 signext %b) { 396; CHECK-LABEL: setnbc23: 397; CHECK: # %bb.0: # %entry 398; CHECK-NEXT: cmpw r3, r4 399; CHECK-NEXT: setnbc r3, gt 400; CHECK-NEXT: blr 401entry: 402 %cmp = icmp sgt i16 %a, %b 403 %sub = sext i1 %cmp to i32 404 ret i32 %sub 405} 406 407define void @setnbc24(i16 signext %a, i16 signext %b) { 408; CHECK-LE-LABEL: setnbc24: 409; CHECK-LE: # %bb.0: # %entry 410; CHECK-LE-NEXT: cmpw r3, r4 411; CHECK-LE-NEXT: setnbc r3, gt 412; CHECK-LE-NEXT: psth r3, globalVal4@PCREL(0), 1 413; CHECK-LE-NEXT: blr 414; 415; CHECK-BE-LABEL: setnbc24: 416; CHECK-BE: # %bb.0: # %entry 417; CHECK-BE-NEXT: cmpw r3, r4 418; CHECK-BE-NEXT: addis r4, r2, .LC3@toc@ha 419; CHECK-BE-NEXT: ld r4, .LC3@toc@l(r4) 420; CHECK-BE-NEXT: setnbc r3, gt 421; CHECK-BE-NEXT: sth r3, 0(r4) 422; CHECK-BE-NEXT: blr 423entry: 424 %cmp = icmp sgt i16 %a, %b 425 %conv3 = sext i1 %cmp to i16 426 store i16 %conv3, i16* @globalVal4, align 2 427 ret void 428} 429 430define signext i32 @setnbc25(i8 zeroext %a, i8 zeroext %b) { 431; CHECK-LABEL: setnbc25: 432; CHECK: # %bb.0: # %entry 433; CHECK-NEXT: cmplw r3, r4 434; CHECK-NEXT: setnbc r3, gt 435; CHECK-NEXT: blr 436entry: 437 %cmp = icmp ugt i8 %a, %b 438 %sub = sext i1 %cmp to i32 439 ret i32 %sub 440} 441 442define void @setnbc26(i8 zeroext %a, i8 zeroext %b) { 443; CHECK-LE-LABEL: setnbc26: 444; CHECK-LE: # %bb.0: # %entry 445; CHECK-LE-NEXT: cmplw r3, r4 446; CHECK-LE-NEXT: setnbc r3, gt 447; CHECK-LE-NEXT: pstb r3, globalVal@PCREL(0), 1 448; CHECK-LE-NEXT: blr 449; 450; CHECK-BE-LABEL: setnbc26: 451; CHECK-BE: # %bb.0: # %entry 452; CHECK-BE-NEXT: cmplw r3, r4 453; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha 454; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) 455; CHECK-BE-NEXT: setnbc r3, gt 456; CHECK-BE-NEXT: stb r3, 0(r4) 457; CHECK-BE-NEXT: blr 458entry: 459 %cmp = icmp ugt i8 %a, %b 460 %conv3 = sext i1 %cmp to i8 461 store i8 %conv3, i8* @globalVal, align 1 462 ret void 463} 464 465define signext i32 @setnbc27(i32 zeroext %a, i32 zeroext %b) { 466; CHECK-LABEL: setnbc27: 467; CHECK: # %bb.0: # %entry 468; CHECK-NEXT: cmplw r3, r4 469; CHECK-NEXT: setnbc r3, gt 470; CHECK-NEXT: blr 471entry: 472 %cmp = icmp ugt i32 %a, %b 473 %sub = sext i1 %cmp to i32 474 ret i32 %sub 475} 476 477define void @setnbc28(i32 zeroext %a, i32 zeroext %b) { 478; CHECK-LE-LABEL: setnbc28: 479; CHECK-LE: # %bb.0: # %entry 480; CHECK-LE-NEXT: cmplw r3, r4 481; CHECK-LE-NEXT: setnbc r3, gt 482; CHECK-LE-NEXT: pstw r3, globalVal2@PCREL(0), 1 483; CHECK-LE-NEXT: blr 484; 485; CHECK-BE-LABEL: setnbc28: 486; CHECK-BE: # %bb.0: # %entry 487; CHECK-BE-NEXT: cmplw r3, r4 488; CHECK-BE-NEXT: addis r4, r2, .LC1@toc@ha 489; CHECK-BE-NEXT: ld r4, .LC1@toc@l(r4) 490; CHECK-BE-NEXT: setnbc r3, gt 491; CHECK-BE-NEXT: stw r3, 0(r4) 492; CHECK-BE-NEXT: blr 493entry: 494 %cmp = icmp ugt i32 %a, %b 495 %sub = sext i1 %cmp to i32 496 store i32 %sub, i32* @globalVal2, align 4 497 ret void 498} 499 500define signext i32 @setnbc29(i16 zeroext %a, i16 zeroext %b) { 501; CHECK-LABEL: setnbc29: 502; CHECK: # %bb.0: # %entry 503; CHECK-NEXT: cmplw r3, r4 504; CHECK-NEXT: setnbc r3, gt 505; CHECK-NEXT: blr 506entry: 507 %cmp = icmp ugt i16 %a, %b 508 %sub = sext i1 %cmp to i32 509 ret i32 %sub 510} 511 512define void @setnbc30(i16 zeroext %a, i16 zeroext %b) { 513; CHECK-LE-LABEL: setnbc30: 514; CHECK-LE: # %bb.0: # %entry 515; CHECK-LE-NEXT: cmplw r3, r4 516; CHECK-LE-NEXT: setnbc r3, gt 517; CHECK-LE-NEXT: psth r3, globalVal4@PCREL(0), 1 518; CHECK-LE-NEXT: blr 519; 520; CHECK-BE-LABEL: setnbc30: 521; CHECK-BE: # %bb.0: # %entry 522; CHECK-BE-NEXT: cmplw r3, r4 523; CHECK-BE-NEXT: addis r4, r2, .LC3@toc@ha 524; CHECK-BE-NEXT: ld r4, .LC3@toc@l(r4) 525; CHECK-BE-NEXT: setnbc r3, gt 526; CHECK-BE-NEXT: sth r3, 0(r4) 527; CHECK-BE-NEXT: blr 528entry: 529 %cmp = icmp ugt i16 %a, %b 530 %conv3 = sext i1 %cmp to i16 531 store i16 %conv3, i16* @globalVal4, align 2 532 ret void 533} 534 535define signext i32 @setnbc31(i8 signext %a, i8 signext %b) { 536; CHECK-LABEL: setnbc31: 537; CHECK: # %bb.0: # %entry 538; CHECK-NEXT: cmpw r3, r4 539; CHECK-NEXT: setnbc r3, lt 540; CHECK-NEXT: blr 541entry: 542 %cmp = icmp slt i8 %a, %b 543 %sub = sext i1 %cmp to i32 544 ret i32 %sub 545} 546 547define void @setnbc32(i8 signext %a, i8 signext %b) { 548; CHECK-LE-LABEL: setnbc32: 549; CHECK-LE: # %bb.0: # %entry 550; CHECK-LE-NEXT: cmpw r3, r4 551; CHECK-LE-NEXT: setnbc r3, lt 552; CHECK-LE-NEXT: pstb r3, globalVal@PCREL(0), 1 553; CHECK-LE-NEXT: blr 554; 555; CHECK-BE-LABEL: setnbc32: 556; CHECK-BE: # %bb.0: # %entry 557; CHECK-BE-NEXT: cmpw r3, r4 558; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha 559; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) 560; CHECK-BE-NEXT: setnbc r3, lt 561; CHECK-BE-NEXT: stb r3, 0(r4) 562; CHECK-BE-NEXT: blr 563entry: 564 %cmp = icmp slt i8 %a, %b 565 %conv3 = sext i1 %cmp to i8 566 store i8 %conv3, i8* @globalVal, align 1 567 ret void 568} 569 570define void @setnbc33(i32 signext %a, i32 signext %b) { 571; CHECK-LE-LABEL: setnbc33: 572; CHECK-LE: # %bb.0: # %entry 573; CHECK-LE-NEXT: cmpw r3, r4 574; CHECK-LE-NEXT: setnbc r3, lt 575; CHECK-LE-NEXT: pstw r3, globalVal2@PCREL(0), 1 576; CHECK-LE-NEXT: blr 577; 578; CHECK-BE-LABEL: setnbc33: 579; CHECK-BE: # %bb.0: # %entry 580; CHECK-BE-NEXT: cmpw r3, r4 581; CHECK-BE-NEXT: addis r4, r2, .LC1@toc@ha 582; CHECK-BE-NEXT: ld r4, .LC1@toc@l(r4) 583; CHECK-BE-NEXT: setnbc r3, lt 584; CHECK-BE-NEXT: stw r3, 0(r4) 585; CHECK-BE-NEXT: blr 586entry: 587 %cmp = icmp slt i32 %a, %b 588 %sub = sext i1 %cmp to i32 589 store i32 %sub, i32* @globalVal2, align 4 590 ret void 591} 592 593define signext i32 @setnbc34(i64 %a, i64 %b) { 594; CHECK-LABEL: setnbc34: 595; CHECK: # %bb.0: # %entry 596; CHECK-NEXT: cmpd r3, r4 597; CHECK-NEXT: setnbc r3, lt 598; CHECK-NEXT: blr 599entry: 600 %cmp = icmp slt i64 %a, %b 601 %sub = sext i1 %cmp to i32 602 ret i32 %sub 603} 604 605define signext i64 @setnbc35(i64 %a, i64 %b) { 606; CHECK-LABEL: setnbc35: 607; CHECK: # %bb.0: # %entry 608; CHECK-NEXT: cmpd r3, r4 609; CHECK-NEXT: setnbc r3, lt 610; CHECK-NEXT: blr 611entry: 612 %cmp = icmp slt i64 %a, %b 613 %sub = sext i1 %cmp to i64 614 ret i64 %sub 615} 616 617define void @setnbc36(i64 %a, i64 %b) { 618; CHECK-LE-LABEL: setnbc36: 619; CHECK-LE: # %bb.0: # %entry 620; CHECK-LE-NEXT: cmpd r3, r4 621; CHECK-LE-NEXT: setnbc r3, lt 622; CHECK-LE-NEXT: pstd r3, globalVal3@PCREL(0), 1 623; CHECK-LE-NEXT: blr 624; 625; CHECK-BE-LABEL: setnbc36: 626; CHECK-BE: # %bb.0: # %entry 627; CHECK-BE-NEXT: cmpd r3, r4 628; CHECK-BE-NEXT: addis r4, r2, .LC2@toc@ha 629; CHECK-BE-NEXT: ld r4, .LC2@toc@l(r4) 630; CHECK-BE-NEXT: setnbc r3, lt 631; CHECK-BE-NEXT: std r3, 0(r4) 632; CHECK-BE-NEXT: blr 633entry: 634 %cmp = icmp slt i64 %a, %b 635 %conv1 = sext i1 %cmp to i64 636 store i64 %conv1, i64* @globalVal3, align 8 637 ret void 638} 639 640define signext i32 @setnbc37(i16 signext %a, i16 signext %b) { 641; CHECK-LABEL: setnbc37: 642; CHECK: # %bb.0: # %entry 643; CHECK-NEXT: cmpw r3, r4 644; CHECK-NEXT: setnbc r3, lt 645; CHECK-NEXT: blr 646entry: 647 %cmp = icmp slt i16 %a, %b 648 %sub = sext i1 %cmp to i32 649 ret i32 %sub 650} 651 652define void @setnbc38(i16 signext %a, i16 signext %b) { 653; CHECK-LE-LABEL: setnbc38: 654; CHECK-LE: # %bb.0: # %entry 655; CHECK-LE-NEXT: cmpw r3, r4 656; CHECK-LE-NEXT: setnbc r3, lt 657; CHECK-LE-NEXT: psth r3, globalVal4@PCREL(0), 1 658; CHECK-LE-NEXT: blr 659; 660; CHECK-BE-LABEL: setnbc38: 661; CHECK-BE: # %bb.0: # %entry 662; CHECK-BE-NEXT: cmpw r3, r4 663; CHECK-BE-NEXT: addis r4, r2, .LC3@toc@ha 664; CHECK-BE-NEXT: ld r4, .LC3@toc@l(r4) 665; CHECK-BE-NEXT: setnbc r3, lt 666; CHECK-BE-NEXT: sth r3, 0(r4) 667; CHECK-BE-NEXT: blr 668entry: 669 %cmp = icmp slt i16 %a, %b 670 %conv3 = sext i1 %cmp to i16 671 store i16 %conv3, i16* @globalVal4, align 2 672 ret void 673} 674 675define signext i32 @setnbc39(i8 zeroext %a, i8 zeroext %b) { 676; CHECK-LABEL: setnbc39: 677; CHECK: # %bb.0: # %entry 678; CHECK-NEXT: cmplw r3, r4 679; CHECK-NEXT: setnbc r3, lt 680; CHECK-NEXT: blr 681entry: 682 %cmp = icmp ult i8 %a, %b 683 %sub = sext i1 %cmp to i32 684 ret i32 %sub 685} 686 687define void @setnbc40(i8 zeroext %a, i8 zeroext %b) { 688; CHECK-LE-LABEL: setnbc40: 689; CHECK-LE: # %bb.0: # %entry 690; CHECK-LE-NEXT: cmplw r3, r4 691; CHECK-LE-NEXT: setnbc r3, lt 692; CHECK-LE-NEXT: pstb r3, globalVal@PCREL(0), 1 693; CHECK-LE-NEXT: blr 694; 695; CHECK-BE-LABEL: setnbc40: 696; CHECK-BE: # %bb.0: # %entry 697; CHECK-BE-NEXT: cmplw r3, r4 698; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha 699; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) 700; CHECK-BE-NEXT: setnbc r3, lt 701; CHECK-BE-NEXT: stb r3, 0(r4) 702; CHECK-BE-NEXT: blr 703entry: 704 %cmp = icmp ult i8 %a, %b 705 %conv3 = sext i1 %cmp to i8 706 store i8 %conv3, i8* @globalVal, align 1 707 ret void 708} 709 710define signext i32 @setnbc41(i32 zeroext %a, i32 zeroext %b) { 711; CHECK-LABEL: setnbc41: 712; CHECK: # %bb.0: # %entry 713; CHECK-NEXT: cmplw r3, r4 714; CHECK-NEXT: setnbc r3, lt 715; CHECK-NEXT: blr 716entry: 717 %cmp = icmp ult i32 %a, %b 718 %sub = sext i1 %cmp to i32 719 ret i32 %sub 720} 721 722define void @setnbc42(i32 zeroext %a, i32 zeroext %b) { 723; CHECK-LE-LABEL: setnbc42: 724; CHECK-LE: # %bb.0: # %entry 725; CHECK-LE-NEXT: cmplw r3, r4 726; CHECK-LE-NEXT: setnbc r3, lt 727; CHECK-LE-NEXT: pstw r3, globalVal2@PCREL(0), 1 728; CHECK-LE-NEXT: blr 729; 730; CHECK-BE-LABEL: setnbc42: 731; CHECK-BE: # %bb.0: # %entry 732; CHECK-BE-NEXT: cmplw r3, r4 733; CHECK-BE-NEXT: addis r4, r2, .LC1@toc@ha 734; CHECK-BE-NEXT: ld r4, .LC1@toc@l(r4) 735; CHECK-BE-NEXT: setnbc r3, lt 736; CHECK-BE-NEXT: stw r3, 0(r4) 737; CHECK-BE-NEXT: blr 738entry: 739 %cmp = icmp ult i32 %a, %b 740 %sub = sext i1 %cmp to i32 741 store i32 %sub, i32* @globalVal2, align 4 742 ret void 743} 744 745define signext i32 @setnbc43(i16 zeroext %a, i16 zeroext %b) { 746; CHECK-LABEL: setnbc43: 747; CHECK: # %bb.0: # %entry 748; CHECK-NEXT: cmplw r3, r4 749; CHECK-NEXT: setnbc r3, lt 750; CHECK-NEXT: blr 751entry: 752 %cmp = icmp ult i16 %a, %b 753 %sub = sext i1 %cmp to i32 754 ret i32 %sub 755} 756 757define void @setnbc44(i16 zeroext %a, i16 zeroext %b) { 758; CHECK-LE-LABEL: setnbc44: 759; CHECK-LE: # %bb.0: # %entry 760; CHECK-LE-NEXT: cmplw r3, r4 761; CHECK-LE-NEXT: setnbc r3, lt 762; CHECK-LE-NEXT: psth r3, globalVal4@PCREL(0), 1 763; CHECK-LE-NEXT: blr 764; 765; CHECK-BE-LABEL: setnbc44: 766; CHECK-BE: # %bb.0: # %entry 767; CHECK-BE-NEXT: cmplw r3, r4 768; CHECK-BE-NEXT: addis r4, r2, .LC3@toc@ha 769; CHECK-BE-NEXT: ld r4, .LC3@toc@l(r4) 770; CHECK-BE-NEXT: setnbc r3, lt 771; CHECK-BE-NEXT: sth r3, 0(r4) 772; CHECK-BE-NEXT: blr 773entry: 774 %cmp = icmp ult i16 %a, %b 775 %conv3 = sext i1 %cmp to i16 776 store i16 %conv3, i16* @globalVal4, align 2 777 ret void 778} 779 780define i64 @setnbc45(i8 signext %a, i8 signext %b) { 781; CHECK-LABEL: setnbc45: 782; CHECK: # %bb.0: # %entry 783; CHECK-NEXT: cmpw r3, r4 784; CHECK-NEXT: setnbc r3, eq 785; CHECK-NEXT: blr 786entry: 787 %cmp = icmp eq i8 %a, %b 788 %conv3 = sext i1 %cmp to i64 789 ret i64 %conv3 790} 791 792define void @setnbc46(i8 signext %a, i8 signext %b) { 793; CHECK-LE-LABEL: setnbc46: 794; CHECK-LE: # %bb.0: # %entry 795; CHECK-LE-NEXT: cmpw r3, r4 796; CHECK-LE-NEXT: setnbc r3, eq 797; CHECK-LE-NEXT: pstb r3, globalVal@PCREL(0), 1 798; CHECK-LE-NEXT: blr 799; 800; CHECK-BE-LABEL: setnbc46: 801; CHECK-BE: # %bb.0: # %entry 802; CHECK-BE-NEXT: cmpw r3, r4 803; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha 804; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) 805; CHECK-BE-NEXT: setnbc r3, eq 806; CHECK-BE-NEXT: stb r3, 0(r4) 807; CHECK-BE-NEXT: blr 808entry: 809 %cmp = icmp eq i8 %a, %b 810 %conv3 = sext i1 %cmp to i8 811 store i8 %conv3, i8* @globalVal, align 1 812 ret void 813} 814 815define i64 @setnbc47(i32 signext %a, i32 signext %b) { 816; CHECK-LABEL: setnbc47: 817; CHECK: # %bb.0: # %entry 818; CHECK-NEXT: cmpw r3, r4 819; CHECK-NEXT: setnbc r3, eq 820; CHECK-NEXT: blr 821entry: 822 %cmp = icmp eq i32 %a, %b 823 %conv1 = sext i1 %cmp to i64 824 ret i64 %conv1 825} 826 827define void @setnbc48(i32 signext %a, i32 signext %b) { 828; CHECK-LE-LABEL: setnbc48: 829; CHECK-LE: # %bb.0: # %entry 830; CHECK-LE-NEXT: cmpw r3, r4 831; CHECK-LE-NEXT: setnbc r3, eq 832; CHECK-LE-NEXT: pstw r3, globalVal2@PCREL(0), 1 833; CHECK-LE-NEXT: blr 834; 835; CHECK-BE-LABEL: setnbc48: 836; CHECK-BE: # %bb.0: # %entry 837; CHECK-BE-NEXT: cmpw r3, r4 838; CHECK-BE-NEXT: addis r4, r2, .LC1@toc@ha 839; CHECK-BE-NEXT: ld r4, .LC1@toc@l(r4) 840; CHECK-BE-NEXT: setnbc r3, eq 841; CHECK-BE-NEXT: stw r3, 0(r4) 842; CHECK-BE-NEXT: blr 843entry: 844 %cmp = icmp eq i32 %a, %b 845 %sub = sext i1 %cmp to i32 846 store i32 %sub, i32* @globalVal2, align 4 847 ret void 848} 849 850define void @setnbc49(i64 %a, i64 %b) { 851; CHECK-LE-LABEL: setnbc49: 852; CHECK-LE: # %bb.0: # %entry 853; CHECK-LE-NEXT: cmpd r3, r4 854; CHECK-LE-NEXT: setnbc r3, eq 855; CHECK-LE-NEXT: pstd r3, globalVal3@PCREL(0), 1 856; CHECK-LE-NEXT: blr 857; 858; CHECK-BE-LABEL: setnbc49: 859; CHECK-BE: # %bb.0: # %entry 860; CHECK-BE-NEXT: cmpd r3, r4 861; CHECK-BE-NEXT: addis r4, r2, .LC2@toc@ha 862; CHECK-BE-NEXT: ld r4, .LC2@toc@l(r4) 863; CHECK-BE-NEXT: setnbc r3, eq 864; CHECK-BE-NEXT: std r3, 0(r4) 865; CHECK-BE-NEXT: blr 866entry: 867 %cmp = icmp eq i64 %a, %b 868 %conv1 = sext i1 %cmp to i64 869 store i64 %conv1, i64* @globalVal3, align 8 870 ret void 871} 872 873define i64 @setnbc50(i16 signext %a, i16 signext %b) { 874; CHECK-LABEL: setnbc50: 875; CHECK: # %bb.0: # %entry 876; CHECK-NEXT: cmpw r3, r4 877; CHECK-NEXT: setnbc r3, eq 878; CHECK-NEXT: blr 879entry: 880 %cmp = icmp eq i16 %a, %b 881 %conv3 = sext i1 %cmp to i64 882 ret i64 %conv3 883} 884 885define void @setnbc51(i16 signext %a, i16 signext %b) { 886; CHECK-LE-LABEL: setnbc51: 887; CHECK-LE: # %bb.0: # %entry 888; CHECK-LE-NEXT: cmpw r3, r4 889; CHECK-LE-NEXT: setnbc r3, eq 890; CHECK-LE-NEXT: psth r3, globalVal4@PCREL(0), 1 891; CHECK-LE-NEXT: blr 892; 893; CHECK-BE-LABEL: setnbc51: 894; CHECK-BE: # %bb.0: # %entry 895; CHECK-BE-NEXT: cmpw r3, r4 896; CHECK-BE-NEXT: addis r4, r2, .LC3@toc@ha 897; CHECK-BE-NEXT: ld r4, .LC3@toc@l(r4) 898; CHECK-BE-NEXT: setnbc r3, eq 899; CHECK-BE-NEXT: sth r3, 0(r4) 900; CHECK-BE-NEXT: blr 901entry: 902 %cmp = icmp eq i16 %a, %b 903 %conv3 = sext i1 %cmp to i16 904 store i16 %conv3, i16* @globalVal4, align 2 905 ret void 906} 907 908define i64 @setnbc52(i8 zeroext %a, i8 zeroext %b) { 909; CHECK-LABEL: setnbc52: 910; CHECK: # %bb.0: # %entry 911; CHECK-NEXT: cmpw r3, r4 912; CHECK-NEXT: setnbc r3, eq 913; CHECK-NEXT: blr 914entry: 915 %cmp = icmp eq i8 %a, %b 916 %conv3 = sext i1 %cmp to i64 917 ret i64 %conv3 918} 919 920define void @setnbc53(i8 zeroext %a, i8 zeroext %b) { 921; CHECK-LE-LABEL: setnbc53: 922; CHECK-LE: # %bb.0: # %entry 923; CHECK-LE-NEXT: cmpw r3, r4 924; CHECK-LE-NEXT: setnbc r3, eq 925; CHECK-LE-NEXT: pstb r3, globalVal@PCREL(0), 1 926; CHECK-LE-NEXT: blr 927; 928; CHECK-BE-LABEL: setnbc53: 929; CHECK-BE: # %bb.0: # %entry 930; CHECK-BE-NEXT: cmpw r3, r4 931; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha 932; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) 933; CHECK-BE-NEXT: setnbc r3, eq 934; CHECK-BE-NEXT: stb r3, 0(r4) 935; CHECK-BE-NEXT: blr 936entry: 937 %cmp = icmp eq i8 %a, %b 938 %conv3 = sext i1 %cmp to i8 939 store i8 %conv3, i8* @globalVal, align 1 940 ret void 941} 942 943define i64 @setnbc54(i32 zeroext %a, i32 zeroext %b) { 944; CHECK-LABEL: setnbc54: 945; CHECK: # %bb.0: # %entry 946; CHECK-NEXT: cmpw r3, r4 947; CHECK-NEXT: setnbc r3, eq 948; CHECK-NEXT: blr 949entry: 950 %cmp = icmp eq i32 %a, %b 951 %conv1 = sext i1 %cmp to i64 952 ret i64 %conv1 953} 954 955define void @setnbc55(i32 zeroext %a, i32 zeroext %b) { 956; CHECK-LE-LABEL: setnbc55: 957; CHECK-LE: # %bb.0: # %entry 958; CHECK-LE-NEXT: cmpw r3, r4 959; CHECK-LE-NEXT: setnbc r3, eq 960; CHECK-LE-NEXT: pstw r3, globalVal2@PCREL(0), 1 961; CHECK-LE-NEXT: blr 962; 963; CHECK-BE-LABEL: setnbc55: 964; CHECK-BE: # %bb.0: # %entry 965; CHECK-BE-NEXT: cmpw r3, r4 966; CHECK-BE-NEXT: addis r4, r2, .LC1@toc@ha 967; CHECK-BE-NEXT: ld r4, .LC1@toc@l(r4) 968; CHECK-BE-NEXT: setnbc r3, eq 969; CHECK-BE-NEXT: stw r3, 0(r4) 970; CHECK-BE-NEXT: blr 971entry: 972 %cmp = icmp eq i32 %a, %b 973 %sub = sext i1 %cmp to i32 974 store i32 %sub, i32* @globalVal2, align 4 975 ret void 976} 977 978define i64 @setnbc56(i64 %a, i64 %b) { 979; CHECK-LABEL: setnbc56: 980; CHECK: # %bb.0: # %entry 981; CHECK-NEXT: cmpd r3, r4 982; CHECK-NEXT: setnbc r3, eq 983; CHECK-NEXT: blr 984entry: 985 %cmp = icmp eq i64 %a, %b 986 %conv1 = sext i1 %cmp to i64 987 ret i64 %conv1 988} 989 990define void @setnbc57(i64 %a, i64 %b) { 991; CHECK-LE-LABEL: setnbc57: 992; CHECK-LE: # %bb.0: # %entry 993; CHECK-LE-NEXT: cmpd r3, r4 994; CHECK-LE-NEXT: setnbc r3, eq 995; CHECK-LE-NEXT: pstd r3, globalVal3@PCREL(0), 1 996; CHECK-LE-NEXT: blr 997; 998; CHECK-BE-LABEL: setnbc57: 999; CHECK-BE: # %bb.0: # %entry 1000; CHECK-BE-NEXT: cmpd r3, r4 1001; CHECK-BE-NEXT: addis r4, r2, .LC2@toc@ha 1002; CHECK-BE-NEXT: ld r4, .LC2@toc@l(r4) 1003; CHECK-BE-NEXT: setnbc r3, eq 1004; CHECK-BE-NEXT: std r3, 0(r4) 1005; CHECK-BE-NEXT: blr 1006entry: 1007 %cmp = icmp eq i64 %a, %b 1008 %conv1 = sext i1 %cmp to i64 1009 store i64 %conv1, i64* @globalVal3, align 8 1010 ret void 1011} 1012 1013define i64 @setnbc58(i16 zeroext %a, i16 zeroext %b) { 1014; CHECK-LABEL: setnbc58: 1015; CHECK: # %bb.0: # %entry 1016; CHECK-NEXT: cmpw r3, r4 1017; CHECK-NEXT: setnbc r3, eq 1018; CHECK-NEXT: blr 1019entry: 1020 %cmp = icmp eq i16 %a, %b 1021 %conv3 = sext i1 %cmp to i64 1022 ret i64 %conv3 1023} 1024 1025define void @setnbc59(i16 zeroext %a, i16 zeroext %b) { 1026; CHECK-LE-LABEL: setnbc59: 1027; CHECK-LE: # %bb.0: # %entry 1028; CHECK-LE-NEXT: cmpw r3, r4 1029; CHECK-LE-NEXT: setnbc r3, eq 1030; CHECK-LE-NEXT: psth r3, globalVal4@PCREL(0), 1 1031; CHECK-LE-NEXT: blr 1032; 1033; CHECK-BE-LABEL: setnbc59: 1034; CHECK-BE: # %bb.0: # %entry 1035; CHECK-BE-NEXT: cmpw r3, r4 1036; CHECK-BE-NEXT: addis r4, r2, .LC3@toc@ha 1037; CHECK-BE-NEXT: ld r4, .LC3@toc@l(r4) 1038; CHECK-BE-NEXT: setnbc r3, eq 1039; CHECK-BE-NEXT: sth r3, 0(r4) 1040; CHECK-BE-NEXT: blr 1041entry: 1042 %cmp = icmp eq i16 %a, %b 1043 %conv3 = sext i1 %cmp to i16 1044 store i16 %conv3, i16* @globalVal4, align 2 1045 ret void 1046} 1047 1048define i64 @setnbc60(i64 %a, i64 %b) { 1049; CHECK-LABEL: setnbc60: 1050; CHECK: # %bb.0: # %entry 1051; CHECK-NEXT: cmpd r3, r4 1052; CHECK-NEXT: setnbc r3, gt 1053; CHECK-NEXT: blr 1054entry: 1055 %cmp = icmp sgt i64 %a, %b 1056 %conv1 = sext i1 %cmp to i64 1057 ret i64 %conv1 1058} 1059 1060define void @setnbc61(i64 %a, i64 %b) { 1061; CHECK-LE-LABEL: setnbc61: 1062; CHECK-LE: # %bb.0: # %entry 1063; CHECK-LE-NEXT: cmpd r3, r4 1064; CHECK-LE-NEXT: setnbc r3, gt 1065; CHECK-LE-NEXT: pstd r3, globalVal3@PCREL(0), 1 1066; CHECK-LE-NEXT: blr 1067; 1068; CHECK-BE-LABEL: setnbc61: 1069; CHECK-BE: # %bb.0: # %entry 1070; CHECK-BE-NEXT: cmpd r3, r4 1071; CHECK-BE-NEXT: addis r4, r2, .LC2@toc@ha 1072; CHECK-BE-NEXT: ld r4, .LC2@toc@l(r4) 1073; CHECK-BE-NEXT: setnbc r3, gt 1074; CHECK-BE-NEXT: std r3, 0(r4) 1075; CHECK-BE-NEXT: blr 1076entry: 1077 %cmp = icmp sgt i64 %a, %b 1078 %conv1 = sext i1 %cmp to i64 1079 store i64 %conv1, i64* @globalVal3, align 8 1080 ret void 1081} 1082 1083define i64 @setnbc62(i8 zeroext %a, i8 zeroext %b) { 1084; CHECK-LABEL: setnbc62: 1085; CHECK: # %bb.0: # %entry 1086; CHECK-NEXT: cmplw r3, r4 1087; CHECK-NEXT: setnbc r3, gt 1088; CHECK-NEXT: blr 1089entry: 1090 %cmp = icmp ugt i8 %a, %b 1091 %conv3 = sext i1 %cmp to i64 1092 ret i64 %conv3 1093} 1094 1095define void @setnbc63(i8 zeroext %a, i8 zeroext %b) { 1096; CHECK-LE-LABEL: setnbc63: 1097; CHECK-LE: # %bb.0: # %entry 1098; CHECK-LE-NEXT: cmplw r3, r4 1099; CHECK-LE-NEXT: setnbc r3, gt 1100; CHECK-LE-NEXT: pstb r3, globalVal@PCREL(0), 1 1101; CHECK-LE-NEXT: blr 1102; 1103; CHECK-BE-LABEL: setnbc63: 1104; CHECK-BE: # %bb.0: # %entry 1105; CHECK-BE-NEXT: cmplw r3, r4 1106; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha 1107; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) 1108; CHECK-BE-NEXT: setnbc r3, gt 1109; CHECK-BE-NEXT: stb r3, 0(r4) 1110; CHECK-BE-NEXT: blr 1111entry: 1112 %cmp = icmp ugt i8 %a, %b 1113 %conv3 = sext i1 %cmp to i8 1114 store i8 %conv3, i8* @globalVal, align 1 1115 ret void 1116} 1117 1118define i64 @setnbc64(i32 zeroext %a, i32 zeroext %b) { 1119; CHECK-LABEL: setnbc64: 1120; CHECK: # %bb.0: # %entry 1121; CHECK-NEXT: cmplw r3, r4 1122; CHECK-NEXT: setnbc r3, gt 1123; CHECK-NEXT: blr 1124entry: 1125 %cmp = icmp ugt i32 %a, %b 1126 %conv1 = sext i1 %cmp to i64 1127 ret i64 %conv1 1128} 1129 1130define void @setnbc65(i32 zeroext %a, i32 zeroext %b) { 1131; CHECK-LE-LABEL: setnbc65: 1132; CHECK-LE: # %bb.0: # %entry 1133; CHECK-LE-NEXT: cmplw r3, r4 1134; CHECK-LE-NEXT: setnbc r3, gt 1135; CHECK-LE-NEXT: pstw r3, globalVal2@PCREL(0), 1 1136; CHECK-LE-NEXT: blr 1137; 1138; CHECK-BE-LABEL: setnbc65: 1139; CHECK-BE: # %bb.0: # %entry 1140; CHECK-BE-NEXT: cmplw r3, r4 1141; CHECK-BE-NEXT: addis r4, r2, .LC1@toc@ha 1142; CHECK-BE-NEXT: ld r4, .LC1@toc@l(r4) 1143; CHECK-BE-NEXT: setnbc r3, gt 1144; CHECK-BE-NEXT: stw r3, 0(r4) 1145; CHECK-BE-NEXT: blr 1146entry: 1147 %cmp = icmp ugt i32 %a, %b 1148 %sub = sext i1 %cmp to i32 1149 store i32 %sub, i32* @globalVal2, align 4 1150 ret void 1151} 1152 1153define i64 @setnbc66(i16 zeroext %a, i16 zeroext %b) { 1154; CHECK-LABEL: setnbc66: 1155; CHECK: # %bb.0: # %entry 1156; CHECK-NEXT: cmplw r3, r4 1157; CHECK-NEXT: setnbc r3, gt 1158; CHECK-NEXT: blr 1159entry: 1160 %cmp = icmp ugt i16 %a, %b 1161 %conv3 = sext i1 %cmp to i64 1162 ret i64 %conv3 1163} 1164 1165define void @setnbc67(i16 zeroext %a, i16 zeroext %b) { 1166; CHECK-LE-LABEL: setnbc67: 1167; CHECK-LE: # %bb.0: # %entry 1168; CHECK-LE-NEXT: cmplw r3, r4 1169; CHECK-LE-NEXT: setnbc r3, gt 1170; CHECK-LE-NEXT: psth r3, globalVal4@PCREL(0), 1 1171; CHECK-LE-NEXT: blr 1172; 1173; CHECK-BE-LABEL: setnbc67: 1174; CHECK-BE: # %bb.0: # %entry 1175; CHECK-BE-NEXT: cmplw r3, r4 1176; CHECK-BE-NEXT: addis r4, r2, .LC3@toc@ha 1177; CHECK-BE-NEXT: ld r4, .LC3@toc@l(r4) 1178; CHECK-BE-NEXT: setnbc r3, gt 1179; CHECK-BE-NEXT: sth r3, 0(r4) 1180; CHECK-BE-NEXT: blr 1181entry: 1182 %cmp = icmp ugt i16 %a, %b 1183 %conv3 = sext i1 %cmp to i16 1184 store i16 %conv3, i16* @globalVal4, align 2 1185 ret void 1186} 1187 1188define i64 @setnbc68(i64 %a, i64 %b) { 1189; CHECK-LABEL: setnbc68: 1190; CHECK: # %bb.0: # %entry 1191; CHECK-NEXT: cmpd r3, r4 1192; CHECK-NEXT: setnbc r3, lt 1193; CHECK-NEXT: blr 1194entry: 1195 %cmp = icmp slt i64 %a, %b 1196 %conv1 = sext i1 %cmp to i64 1197 ret i64 %conv1 1198} 1199 1200define void @setnbc69(i64 %a, i64 %b) { 1201; CHECK-LE-LABEL: setnbc69: 1202; CHECK-LE: # %bb.0: # %entry 1203; CHECK-LE-NEXT: cmpd r3, r4 1204; CHECK-LE-NEXT: setnbc r3, lt 1205; CHECK-LE-NEXT: pstd r3, globalVal3@PCREL(0), 1 1206; CHECK-LE-NEXT: blr 1207; 1208; CHECK-BE-LABEL: setnbc69: 1209; CHECK-BE: # %bb.0: # %entry 1210; CHECK-BE-NEXT: cmpd r3, r4 1211; CHECK-BE-NEXT: addis r4, r2, .LC2@toc@ha 1212; CHECK-BE-NEXT: ld r4, .LC2@toc@l(r4) 1213; CHECK-BE-NEXT: setnbc r3, lt 1214; CHECK-BE-NEXT: std r3, 0(r4) 1215; CHECK-BE-NEXT: blr 1216entry: 1217 %cmp = icmp slt i64 %a, %b 1218 %conv1 = sext i1 %cmp to i64 1219 store i64 %conv1, i64* @globalVal3, align 8 1220 ret void 1221} 1222 1223define i64 @setnbc70(i8 zeroext %a, i8 zeroext %b) { 1224; CHECK-LABEL: setnbc70: 1225; CHECK: # %bb.0: # %entry 1226; CHECK-NEXT: cmplw r3, r4 1227; CHECK-NEXT: setnbc r3, lt 1228; CHECK-NEXT: blr 1229entry: 1230 %cmp = icmp ult i8 %a, %b 1231 %conv3 = sext i1 %cmp to i64 1232 ret i64 %conv3 1233} 1234 1235define void @setnbc71(i8 zeroext %a, i8 zeroext %b) { 1236; CHECK-LE-LABEL: setnbc71: 1237; CHECK-LE: # %bb.0: # %entry 1238; CHECK-LE-NEXT: cmplw r3, r4 1239; CHECK-LE-NEXT: setnbc r3, lt 1240; CHECK-LE-NEXT: pstb r3, globalVal@PCREL(0), 1 1241; CHECK-LE-NEXT: blr 1242; 1243; CHECK-BE-LABEL: setnbc71: 1244; CHECK-BE: # %bb.0: # %entry 1245; CHECK-BE-NEXT: cmplw r3, r4 1246; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha 1247; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) 1248; CHECK-BE-NEXT: setnbc r3, lt 1249; CHECK-BE-NEXT: stb r3, 0(r4) 1250; CHECK-BE-NEXT: blr 1251entry: 1252 %cmp = icmp ult i8 %a, %b 1253 %conv3 = sext i1 %cmp to i8 1254 store i8 %conv3, i8* @globalVal, align 1 1255 ret void 1256} 1257 1258define i64 @setnbc72(i32 zeroext %a, i32 zeroext %b) { 1259; CHECK-LABEL: setnbc72: 1260; CHECK: # %bb.0: # %entry 1261; CHECK-NEXT: cmplw r3, r4 1262; CHECK-NEXT: setnbc r3, lt 1263; CHECK-NEXT: blr 1264entry: 1265 %cmp = icmp ult i32 %a, %b 1266 %conv1 = sext i1 %cmp to i64 1267 ret i64 %conv1 1268} 1269 1270define void @setnbc73(i32 zeroext %a, i32 zeroext %b) { 1271; CHECK-LE-LABEL: setnbc73: 1272; CHECK-LE: # %bb.0: # %entry 1273; CHECK-LE-NEXT: cmplw r3, r4 1274; CHECK-LE-NEXT: setnbc r3, lt 1275; CHECK-LE-NEXT: pstw r3, globalVal2@PCREL(0), 1 1276; CHECK-LE-NEXT: blr 1277; 1278; CHECK-BE-LABEL: setnbc73: 1279; CHECK-BE: # %bb.0: # %entry 1280; CHECK-BE-NEXT: cmplw r3, r4 1281; CHECK-BE-NEXT: addis r4, r2, .LC1@toc@ha 1282; CHECK-BE-NEXT: ld r4, .LC1@toc@l(r4) 1283; CHECK-BE-NEXT: setnbc r3, lt 1284; CHECK-BE-NEXT: stw r3, 0(r4) 1285; CHECK-BE-NEXT: blr 1286entry: 1287 %cmp = icmp ult i32 %a, %b 1288 %sub = sext i1 %cmp to i32 1289 store i32 %sub, i32* @globalVal2, align 4 1290 ret void 1291} 1292 1293define i64 @setnbc74(i16 zeroext %a, i16 zeroext %b) { 1294; CHECK-LABEL: setnbc74: 1295; CHECK: # %bb.0: # %entry 1296; CHECK-NEXT: cmplw r3, r4 1297; CHECK-NEXT: setnbc r3, lt 1298; CHECK-NEXT: blr 1299entry: 1300 %cmp = icmp ult i16 %a, %b 1301 %conv3 = sext i1 %cmp to i64 1302 ret i64 %conv3 1303} 1304 1305define void @setnbc75(i16 zeroext %a, i16 zeroext %b) { 1306; CHECK-LE-LABEL: setnbc75: 1307; CHECK-LE: # %bb.0: # %entry 1308; CHECK-LE-NEXT: cmplw r3, r4 1309; CHECK-LE-NEXT: setnbc r3, lt 1310; CHECK-LE-NEXT: psth r3, globalVal4@PCREL(0), 1 1311; CHECK-LE-NEXT: blr 1312; 1313; CHECK-BE-LABEL: setnbc75: 1314; CHECK-BE: # %bb.0: # %entry 1315; CHECK-BE-NEXT: cmplw r3, r4 1316; CHECK-BE-NEXT: addis r4, r2, .LC3@toc@ha 1317; CHECK-BE-NEXT: ld r4, .LC3@toc@l(r4) 1318; CHECK-BE-NEXT: setnbc r3, lt 1319; CHECK-BE-NEXT: sth r3, 0(r4) 1320; CHECK-BE-NEXT: blr 1321entry: 1322 %cmp = icmp ult i16 %a, %b 1323 %conv3 = sext i1 %cmp to i16 1324 store i16 %conv3, i16* @globalVal4, align 2 1325 ret void 1326} 1327 1328