1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ 3; RUN: -ppc-asm-full-reg-names -mcpu=pwr10 < %s | FileCheck %s \ 4; RUN: --check-prefixes=CHECK,CHECK-LE 5; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ 6; RUN: -ppc-asm-full-reg-names -mcpu=pwr10 < %s | FileCheck %s \ 7; RUN: --check-prefixes=CHECK,CHECK-BE 8 9; This file does not contain many test cases involving comparisons and logical 10; comparisons (cmplwi, cmpldi). This is because alternative code is generated 11; when there is a compare (logical or not), followed by a sign or zero extend. 12; This codegen will be re-evaluated at a later time on whether or not it should 13; be emitted on P10. 14 15@globalVal = common local_unnamed_addr global i8 0, align 1 16@globalVal2 = common local_unnamed_addr global i32 0, align 4 17@globalVal3 = common local_unnamed_addr global i64 0, align 8 18@globalVal4 = common local_unnamed_addr global i16 0, align 2 19 20define signext i32 @setnbcr1(i8 %a) { 21; CHECK-LABEL: setnbcr1: 22; CHECK: # %bb.0: # %entry 23; CHECK-NEXT: andi. r3, r3, 255 24; CHECK-NEXT: setnbcr r3, eq 25; CHECK-NEXT: blr 26entry: 27 %cmp = icmp uge i8 %a, 1 28 %conv = sext i1 %cmp to i32 29 ret i32 %conv 30} 31 32define signext i32 @setnbcr2(i32 %a) { 33; CHECK-LABEL: setnbcr2: 34; CHECK: # %bb.0: # %entry 35; CHECK-NEXT: cmpwi r3, 0 36; CHECK-NEXT: setnbcr r3, eq 37; CHECK-NEXT: blr 38entry: 39 %cmp = icmp uge i32 %a, 1 40 %conv = sext i1 %cmp to i32 41 ret i32 %conv 42} 43 44define signext i32 @setnbcr3(i64 %a) { 45; CHECK-LABEL: setnbcr3: 46; CHECK: # %bb.0: # %entry 47; CHECK-NEXT: cmpdi r3, 0 48; CHECK-NEXT: setnbcr r3, eq 49; CHECK-NEXT: blr 50entry: 51 %cmp = icmp uge i64 %a, 1 52 %conv = sext i1 %cmp to i32 53 ret i32 %conv 54} 55 56define signext i32 @setnbcr4(i16 %a) { 57; CHECK-LABEL: setnbcr4: 58; CHECK: # %bb.0: # %entry 59; CHECK-NEXT: andi. r3, r3, 65535 60; CHECK-NEXT: setnbcr r3, eq 61; CHECK-NEXT: blr 62entry: 63 %cmp = icmp uge i16 %a, 1 64 %conv = sext i1 %cmp to i32 65 ret i32 %conv 66} 67 68define signext i64 @setnbcr5(i8 %a) { 69; CHECK-LABEL: setnbcr5: 70; CHECK: # %bb.0: # %entry 71; CHECK-NEXT: andi. r3, r3, 255 72; CHECK-NEXT: setnbcr r3, eq 73; CHECK-NEXT: blr 74entry: 75 %cmp = icmp uge i8 %a, 1 76 %conv = sext i1 %cmp to i64 77 ret i64 %conv 78} 79 80define signext i64 @setnbcr6(i32 %a) { 81; CHECK-LABEL: setnbcr6: 82; CHECK: # %bb.0: # %entry 83; CHECK-NEXT: cmpwi r3, 0 84; CHECK-NEXT: setnbcr r3, eq 85; CHECK-NEXT: blr 86entry: 87 %cmp = icmp uge i32 %a, 1 88 %conv = sext i1 %cmp to i64 89 ret i64 %conv 90} 91 92define signext i64 @setnbcr7(i64 %a) { 93; CHECK-LABEL: setnbcr7: 94; CHECK: # %bb.0: # %entry 95; CHECK-NEXT: cmpdi r3, 0 96; CHECK-NEXT: setnbcr r3, eq 97; CHECK-NEXT: blr 98entry: 99 %cmp = icmp uge i64 %a, 1 100 %conv = sext i1 %cmp to i64 101 ret i64 %conv 102} 103 104define signext i64 @setnbcr8(i16 %a) { 105; CHECK-LABEL: setnbcr8: 106; CHECK: # %bb.0: # %entry 107; CHECK-NEXT: andi. r3, r3, 65535 108; CHECK-NEXT: setnbcr r3, eq 109; CHECK-NEXT: blr 110entry: 111 %cmp = icmp uge i16 %a, 1 112 %conv = sext i1 %cmp to i64 113 ret i64 %conv 114} 115 116define void @setnbcr9(i8 %a) { 117; CHECK-LE-LABEL: setnbcr9: 118; CHECK-LE: # %bb.0: # %entry 119; CHECK-LE-NEXT: andi. r3, r3, 255 120; CHECK-LE-NEXT: setnbcr r3, eq 121; CHECK-LE-NEXT: pstb r3, globalVal@PCREL(0), 1 122; CHECK-LE-NEXT: blr 123; 124; CHECK-BE-LABEL: setnbcr9: 125; CHECK-BE: # %bb.0: # %entry 126; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha 127; CHECK-BE-NEXT: andi. r3, r3, 255 128; CHECK-BE-NEXT: setnbcr r3, eq 129; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) 130; CHECK-BE-NEXT: stb r3, 0(r4) 131; CHECK-BE-NEXT: blr 132entry: 133 %cmp = icmp uge i8 %a, 1 134 %conv1 = sext i1 %cmp to i8 135 store i8 %conv1, i8* @globalVal, align 1 136 ret void 137} 138 139define void @setnbcr10(i32 %a) { 140; CHECK-LE-LABEL: setnbcr10: 141; CHECK-LE: # %bb.0: # %entry 142; CHECK-LE-NEXT: cmpwi r3, 0 143; CHECK-LE-NEXT: setnbcr r3, eq 144; CHECK-LE-NEXT: pstw r3, globalVal2@PCREL(0), 1 145; CHECK-LE-NEXT: blr 146; 147; CHECK-BE-LABEL: setnbcr10: 148; CHECK-BE: # %bb.0: # %entry 149; CHECK-BE-NEXT: addis r4, r2, .LC1@toc@ha 150; CHECK-BE-NEXT: cmpwi r3, 0 151; CHECK-BE-NEXT: ld r4, .LC1@toc@l(r4) 152; CHECK-BE-NEXT: setnbcr r3, eq 153; CHECK-BE-NEXT: stw r3, 0(r4) 154; CHECK-BE-NEXT: blr 155entry: 156 %cmp = icmp uge i32 %a, 1 157 %conv1 = sext i1 %cmp to i32 158 store i32 %conv1, i32* @globalVal2, align 4 159 ret void 160} 161 162define void @setnbcr11(i64 %a) { 163; CHECK-LE-LABEL: setnbcr11: 164; CHECK-LE: # %bb.0: # %entry 165; CHECK-LE-NEXT: cmpdi r3, 0 166; CHECK-LE-NEXT: setnbcr r3, eq 167; CHECK-LE-NEXT: pstd r3, globalVal3@PCREL(0), 1 168; CHECK-LE-NEXT: blr 169; 170; CHECK-BE-LABEL: setnbcr11: 171; CHECK-BE: # %bb.0: # %entry 172; CHECK-BE-NEXT: addis r4, r2, .LC2@toc@ha 173; CHECK-BE-NEXT: cmpdi r3, 0 174; CHECK-BE-NEXT: ld r4, .LC2@toc@l(r4) 175; CHECK-BE-NEXT: setnbcr r3, eq 176; CHECK-BE-NEXT: std r3, 0(r4) 177; CHECK-BE-NEXT: blr 178entry: 179 %cmp = icmp uge i64 %a, 1 180 %conv1 = sext i1 %cmp to i64 181 store i64 %conv1, i64* @globalVal3, align 8 182 ret void 183} 184 185define void @setnbcr12(i16 %a) { 186; CHECK-LE-LABEL: setnbcr12: 187; CHECK-LE: # %bb.0: # %entry 188; CHECK-LE-NEXT: andi. r3, r3, 65535 189; CHECK-LE-NEXT: setnbcr r3, eq 190; CHECK-LE-NEXT: psth r3, globalVal4@PCREL(0), 1 191; CHECK-LE-NEXT: blr 192; 193; CHECK-BE-LABEL: setnbcr12: 194; CHECK-BE: # %bb.0: # %entry 195; CHECK-BE-NEXT: addis r4, r2, .LC3@toc@ha 196; CHECK-BE-NEXT: andi. r3, r3, 65535 197; CHECK-BE-NEXT: setnbcr r3, eq 198; CHECK-BE-NEXT: ld r4, .LC3@toc@l(r4) 199; CHECK-BE-NEXT: sth r3, 0(r4) 200; CHECK-BE-NEXT: blr 201entry: 202 %cmp = icmp uge i16 %a, 1 203 %conv1 = sext i1 %cmp to i16 204 store i16 %conv1, i16* @globalVal4, align 2 205 ret void 206} 207 208define signext i32 @setnbcr13(i8 %a) { 209; CHECK-LABEL: setnbcr13: 210; CHECK: # %bb.0: # %entry 211; CHECK-NEXT: clrlwi r3, r3, 24 212; CHECK-NEXT: cmpwi r3, 1 213; CHECK-NEXT: setnbcr r3, eq 214; CHECK-NEXT: blr 215entry: 216 %cmp = icmp ne i8 %a, 1 217 %conv = sext i1 %cmp to i32 218 ret i32 %conv 219} 220 221define signext i32 @setnbcr14(i32 %a) { 222; CHECK-LABEL: setnbcr14: 223; CHECK: # %bb.0: # %entry 224; CHECK-NEXT: cmpwi r3, 1 225; CHECK-NEXT: setnbcr r3, eq 226; CHECK-NEXT: blr 227entry: 228 %cmp = icmp ne i32 %a, 1 229 %conv = sext i1 %cmp to i32 230 ret i32 %conv 231} 232 233define signext i32 @setnbcr15(i64 %a) { 234; CHECK-LABEL: setnbcr15: 235; CHECK: # %bb.0: # %entry 236; CHECK-NEXT: cmpdi r3, 1 237; CHECK-NEXT: setnbcr r3, eq 238; CHECK-NEXT: blr 239entry: 240 %cmp = icmp ne i64 %a, 1 241 %conv = sext i1 %cmp to i32 242 ret i32 %conv 243} 244 245define signext i32 @setnbcr16(i16 %a) { 246; CHECK-LABEL: setnbcr16: 247; CHECK: # %bb.0: # %entry 248; CHECK-NEXT: clrlwi r3, r3, 16 249; CHECK-NEXT: cmpwi r3, 1 250; CHECK-NEXT: setnbcr r3, eq 251; CHECK-NEXT: blr 252entry: 253 %cmp = icmp ne i16 %a, 1 254 %conv = sext i1 %cmp to i32 255 ret i32 %conv 256} 257 258define signext i64 @setnbcr17(i8 %a) { 259; CHECK-LABEL: setnbcr17: 260; CHECK: # %bb.0: # %entry 261; CHECK-NEXT: clrlwi r3, r3, 24 262; CHECK-NEXT: cmpwi r3, 1 263; CHECK-NEXT: setnbcr r3, eq 264; CHECK-NEXT: blr 265entry: 266 %cmp = icmp ne i8 %a, 1 267 %conv = sext i1 %cmp to i64 268 ret i64 %conv 269} 270 271define signext i64 @setnbcr18(i32 %a) { 272; CHECK-LABEL: setnbcr18: 273; CHECK: # %bb.0: # %entry 274; CHECK-NEXT: cmpwi r3, 1 275; CHECK-NEXT: setnbcr r3, eq 276; CHECK-NEXT: blr 277entry: 278 %cmp = icmp ne i32 %a, 1 279 %conv = sext i1 %cmp to i64 280 ret i64 %conv 281} 282 283define signext i64 @setnbcr19(i64 %a) { 284; CHECK-LABEL: setnbcr19: 285; CHECK: # %bb.0: # %entry 286; CHECK-NEXT: cmpdi r3, 1 287; CHECK-NEXT: setnbcr r3, eq 288; CHECK-NEXT: blr 289entry: 290 %cmp = icmp ne i64 %a, 1 291 %conv = sext i1 %cmp to i64 292 ret i64 %conv 293} 294 295define signext i64 @setnbcr20(i16 %a) { 296; CHECK-LABEL: setnbcr20: 297; CHECK: # %bb.0: # %entry 298; CHECK-NEXT: clrlwi r3, r3, 16 299; CHECK-NEXT: cmpwi r3, 1 300; CHECK-NEXT: setnbcr r3, eq 301; CHECK-NEXT: blr 302entry: 303 %cmp = icmp ne i16 %a, 1 304 %conv = sext i1 %cmp to i64 305 ret i64 %conv 306} 307 308define void @setnbcr21(i8 %a) { 309; CHECK-LE-LABEL: setnbcr21: 310; CHECK-LE: # %bb.0: # %entry 311; CHECK-LE-NEXT: clrlwi r3, r3, 24 312; CHECK-LE-NEXT: cmpwi r3, 1 313; CHECK-LE-NEXT: setnbcr r3, eq 314; CHECK-LE-NEXT: pstb r3, globalVal@PCREL(0), 1 315; CHECK-LE-NEXT: blr 316; 317; CHECK-BE-LABEL: setnbcr21: 318; CHECK-BE: # %bb.0: # %entry 319; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha 320; CHECK-BE-NEXT: clrlwi r3, r3, 24 321; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) 322; CHECK-BE-NEXT: cmpwi r3, 1 323; CHECK-BE-NEXT: setnbcr r3, eq 324; CHECK-BE-NEXT: stb r3, 0(r4) 325; CHECK-BE-NEXT: blr 326entry: 327 %cmp = icmp ne i8 %a, 1 328 %conv1 = sext i1 %cmp to i8 329 store i8 %conv1, i8* @globalVal, align 1 330 ret void 331} 332 333define void @setnbcr22(i32 %a) { 334; CHECK-LE-LABEL: setnbcr22: 335; CHECK-LE: # %bb.0: # %entry 336; CHECK-LE-NEXT: cmpwi r3, 1 337; CHECK-LE-NEXT: setnbcr r3, eq 338; CHECK-LE-NEXT: pstw r3, globalVal2@PCREL(0), 1 339; CHECK-LE-NEXT: blr 340; 341; CHECK-BE-LABEL: setnbcr22: 342; CHECK-BE: # %bb.0: # %entry 343; CHECK-BE-NEXT: addis r4, r2, .LC1@toc@ha 344; CHECK-BE-NEXT: cmpwi r3, 1 345; CHECK-BE-NEXT: ld r4, .LC1@toc@l(r4) 346; CHECK-BE-NEXT: setnbcr r3, eq 347; CHECK-BE-NEXT: stw r3, 0(r4) 348; CHECK-BE-NEXT: blr 349entry: 350 %cmp = icmp ne i32 %a, 1 351 %conv1 = sext i1 %cmp to i32 352 store i32 %conv1, i32* @globalVal2, align 4 353 ret void 354} 355 356define void @setnbcr23(i64 %a) { 357; CHECK-LE-LABEL: setnbcr23: 358; CHECK-LE: # %bb.0: # %entry 359; CHECK-LE-NEXT: cmpdi r3, 1 360; CHECK-LE-NEXT: setnbcr r3, eq 361; CHECK-LE-NEXT: pstd r3, globalVal3@PCREL(0), 1 362; CHECK-LE-NEXT: blr 363; 364; CHECK-BE-LABEL: setnbcr23: 365; CHECK-BE: # %bb.0: # %entry 366; CHECK-BE-NEXT: addis r4, r2, .LC2@toc@ha 367; CHECK-BE-NEXT: cmpdi r3, 1 368; CHECK-BE-NEXT: ld r4, .LC2@toc@l(r4) 369; CHECK-BE-NEXT: setnbcr r3, eq 370; CHECK-BE-NEXT: std r3, 0(r4) 371; CHECK-BE-NEXT: blr 372entry: 373 %cmp = icmp ne i64 %a, 1 374 %conv1 = sext i1 %cmp to i64 375 store i64 %conv1, i64* @globalVal3, align 8 376 ret void 377} 378 379define void @setnbcr24(i16 %a) { 380; CHECK-LE-LABEL: setnbcr24: 381; CHECK-LE: # %bb.0: # %entry 382; CHECK-LE-NEXT: clrlwi r3, r3, 16 383; CHECK-LE-NEXT: cmpwi r3, 1 384; CHECK-LE-NEXT: setnbcr r3, eq 385; CHECK-LE-NEXT: psth r3, globalVal4@PCREL(0), 1 386; CHECK-LE-NEXT: blr 387; 388; CHECK-BE-LABEL: setnbcr24: 389; CHECK-BE: # %bb.0: # %entry 390; CHECK-BE-NEXT: addis r4, r2, .LC3@toc@ha 391; CHECK-BE-NEXT: clrlwi r3, r3, 16 392; CHECK-BE-NEXT: ld r4, .LC3@toc@l(r4) 393; CHECK-BE-NEXT: cmpwi r3, 1 394; CHECK-BE-NEXT: setnbcr r3, eq 395; CHECK-BE-NEXT: sth r3, 0(r4) 396; CHECK-BE-NEXT: blr 397entry: 398 %cmp = icmp ne i16 %a, 1 399 %conv1 = sext i1 %cmp to i16 400 store i16 %conv1, i16* @globalVal4, align 2 401 ret void 402} 403 404