1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
3; RUN:     -ppc-asm-full-reg-names -mcpu=pwr10 < %s | \
4; RUN:     FileCheck --check-prefix=CHECK-LE %s
5; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
6; RUN:     -ppc-asm-full-reg-names -mcpu=pwr10 < %s | \
7; RUN:     FileCheck --check-prefix=CHECK-BE %s
8
9; Function Attrs: norecurse nounwind readnone
10define  <4 x i32> @test_xxsplti32dx_1(<4 x i32> %a) {
11; CHECK-LE-LABEL: test_xxsplti32dx_1:
12; CHECK-LE:       # %bb.0: # %entry
13; CHECK-LE-NEXT:    xxsplti32dx vs34, 0, 566
14; CHECK-LE-NEXT:    blr
15;
16; CHECK-BE-LABEL: test_xxsplti32dx_1:
17; CHECK-BE:       # %bb.0: # %entry
18; CHECK-BE-NEXT:    xxsplti32dx vs34, 1, 566
19; CHECK-BE-NEXT:    blr
20entry:
21  %vecins1 = shufflevector <4 x i32> %a, <4 x i32> <i32 undef, i32 566, i32 undef, i32 566>, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
22  ret <4 x i32> %vecins1
23}
24
25; Function Attrs: norecurse nounwind readnone
26define  <4 x i32> @test_xxsplti32dx_2(<4 x i32> %a) {
27; CHECK-LE-LABEL: test_xxsplti32dx_2:
28; CHECK-LE:       # %bb.0: # %entry
29; CHECK-LE-NEXT:    xxsplti32dx vs34, 1, 33
30; CHECK-LE-NEXT:    blr
31;
32; CHECK-BE-LABEL: test_xxsplti32dx_2:
33; CHECK-BE:       # %bb.0: # %entry
34; CHECK-BE-NEXT:    xxsplti32dx vs34, 0, 33
35; CHECK-BE-NEXT:    blr
36entry:
37  %vecins1 = shufflevector <4 x i32> <i32 33, i32 undef, i32 33, i32 undef>, <4 x i32> %a, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
38  ret <4 x i32> %vecins1
39}
40
41; Function Attrs: norecurse nounwind readnone
42define  <4 x i32> @test_xxsplti32dx_3(<4 x i32> %a) {
43; CHECK-LE-LABEL: test_xxsplti32dx_3:
44; CHECK-LE:       # %bb.0: # %entry
45; CHECK-LE-NEXT:    xxsplti32dx vs34, 0, 12
46; CHECK-LE-NEXT:    blr
47;
48; CHECK-BE-LABEL: test_xxsplti32dx_3:
49; CHECK-BE:       # %bb.0: # %entry
50; CHECK-BE-NEXT:    xxsplti32dx vs34, 1, 12
51; CHECK-BE-NEXT:    blr
52entry:
53  %vecins1 = shufflevector <4 x i32> %a, <4 x i32> <i32 undef, i32 12, i32 undef, i32 12>, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
54  ret <4 x i32> %vecins1
55}
56
57; Function Attrs: norecurse nounwind readnone
58define  <4 x i32> @test_xxsplti32dx_4(<4 x i32> %a) {
59; CHECK-LE-LABEL: test_xxsplti32dx_4:
60; CHECK-LE:       # %bb.0: # %entry
61; CHECK-LE-NEXT:    xxsplti32dx vs34, 1, -683
62; CHECK-LE-NEXT:    blr
63;
64; CHECK-BE-LABEL: test_xxsplti32dx_4:
65; CHECK-BE:       # %bb.0: # %entry
66; CHECK-BE-NEXT:    xxsplti32dx vs34, 0, -683
67; CHECK-BE-NEXT:    blr
68entry:
69  %vecins1 = shufflevector <4 x i32> <i32 -683, i32 undef, i32 -683, i32 undef>, <4 x i32> %a, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
70  ret <4 x i32> %vecins1
71}
72
73; Function Attrs: nounwind
74define  <4 x float> @test_xxsplti32dx_5(<4 x float> %vfa) {
75; CHECK-LE-LABEL: test_xxsplti32dx_5:
76; CHECK-LE:       # %bb.0: # %entry
77; CHECK-LE-NEXT:    xxsplti32dx vs34, 0, 1065353216
78; CHECK-LE-NEXT:    blr
79;
80; CHECK-BE-LABEL: test_xxsplti32dx_5:
81; CHECK-BE:       # %bb.0: # %entry
82; CHECK-BE-NEXT:    xxsplti32dx vs34, 1, 1065353216
83; CHECK-BE-NEXT:    blr
84entry:
85  %vecins3.i = shufflevector <4 x float> %vfa, <4 x float> <float undef, float 1.000000e+00, float undef, float 1.000000e+00>, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
86  ret <4 x float> %vecins3.i
87}
88
89; Function Attrs: nounwind
90define  <4 x float> @test_xxsplti32dx_6(<4 x float> %vfa) {
91; CHECK-LE-LABEL: test_xxsplti32dx_6:
92; CHECK-LE:       # %bb.0: # %entry
93; CHECK-LE-NEXT:    xxsplti32dx vs34, 1, 1073741824
94; CHECK-LE-NEXT:    blr
95;
96; CHECK-BE-LABEL: test_xxsplti32dx_6:
97; CHECK-BE:       # %bb.0: # %entry
98; CHECK-BE-NEXT:    xxsplti32dx vs34, 0, 1073741824
99; CHECK-BE-NEXT:    blr
100entry:
101  %vecins3.i = shufflevector <4 x float> <float 2.000000e+00, float undef, float 2.000000e+00, float undef>, <4 x float> %vfa, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
102  ret <4 x float> %vecins3.i
103}
104
105; Function Attrs: norecurse nounwind readnone
106; Test to illustrate when the splat is narrower than 32-bits.
107define dso_local <4 x i32> @test_xxsplti32dx_7(<4 x i32> %a) local_unnamed_addr #0 {
108; CHECK-LE-LABEL: test_xxsplti32dx_7:
109; CHECK-LE:       # %bb.0: # %entry
110; CHECK-LE-NEXT:    xxsplti32dx vs34, 1, -1414812757
111; CHECK-LE-NEXT:    blr
112;
113; CHECK-BE-LABEL: test_xxsplti32dx_7:
114; CHECK-BE:       # %bb.0: # %entry
115; CHECK-BE-NEXT:    xxsplti32dx vs34, 0, -1414812757
116; CHECK-BE-NEXT:    blr
117entry:
118  %vecins1 = shufflevector <4 x i32> <i32 -1414812757, i32 undef, i32 -1414812757, i32 undef>, <4 x i32> %a, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
119  ret <4 x i32> %vecins1
120}
121