1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs \
3; RUN:   -mtriple=powerpc64le-linux-gnu < %s | FileCheck \
4; RUN:   -check-prefix=CHECK-LE %s
5; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs \
6; RUN:   -mtriple=powerpc64le-linux-gnu -mcpu=pwr9 < %s | FileCheck \
7; RUN:   -check-prefix=CHECK-P9-LE %s
8; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs \
9; RUN:   -mtriple=powerpc64-linux-gnu < %s | FileCheck \
10; RUN:   -check-prefix=CHECK-BE %s
11; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs \
12; RUN:   -mtriple=powerpc-linux-gnu < %s | FileCheck \
13; RUN:   -check-prefix=CHECK-32 %s
14
15define i32 @foo(i32 %n) local_unnamed_addr #0 "stack-probe-size"="32768" nounwind {
16; CHECK-LE-LABEL: foo:
17; CHECK-LE:       # %bb.0:
18; CHECK-LE-NEXT:    std r31, -8(r1)
19; CHECK-LE-NEXT:    stdu r1, -48(r1)
20; CHECK-LE-NEXT:    rldic r3, r3, 2, 30
21; CHECK-LE-NEXT:    li r5, -32768
22; CHECK-LE-NEXT:    mr r31, r1
23; CHECK-LE-NEXT:    addi r3, r3, 15
24; CHECK-LE-NEXT:    rldicl r3, r3, 60, 4
25; CHECK-LE-NEXT:    rldicl r3, r3, 4, 29
26; CHECK-LE-NEXT:    neg r4, r3
27; CHECK-LE-NEXT:    addi r3, r31, 48
28; CHECK-LE-NEXT:    divd r6, r4, r5
29; CHECK-LE-NEXT:    mulld r5, r6, r5
30; CHECK-LE-NEXT:    sub r5, r4, r5
31; CHECK-LE-NEXT:    add r4, r1, r4
32; CHECK-LE-NEXT:    stdux r3, r1, r5
33; CHECK-LE-NEXT:    cmpd r1, r4
34; CHECK-LE-NEXT:    beq cr0, .LBB0_2
35; CHECK-LE-NEXT:  .LBB0_1:
36; CHECK-LE-NEXT:    stdu r3, -32768(r1)
37; CHECK-LE-NEXT:    cmpd r1, r4
38; CHECK-LE-NEXT:    bne cr0, .LBB0_1
39; CHECK-LE-NEXT:  .LBB0_2:
40; CHECK-LE-NEXT:    li r4, 1
41; CHECK-LE-NEXT:    addi r3, r1, 32
42; CHECK-LE-NEXT:    stw r4, 4792(r3)
43; CHECK-LE-NEXT:    lwz r3, 0(r3)
44; CHECK-LE-NEXT:    ld r1, 0(r1)
45; CHECK-LE-NEXT:    ld r31, -8(r1)
46; CHECK-LE-NEXT:    blr
47;
48; CHECK-P9-LE-LABEL: foo:
49; CHECK-P9-LE:       # %bb.0:
50; CHECK-P9-LE-NEXT:    std r31, -8(r1)
51; CHECK-P9-LE-NEXT:    stdu r1, -48(r1)
52; CHECK-P9-LE-NEXT:    rldic r3, r3, 2, 30
53; CHECK-P9-LE-NEXT:    addi r3, r3, 15
54; CHECK-P9-LE-NEXT:    li r6, -32768
55; CHECK-P9-LE-NEXT:    mr r31, r1
56; CHECK-P9-LE-NEXT:    rldicl r3, r3, 60, 4
57; CHECK-P9-LE-NEXT:    rldicl r3, r3, 4, 29
58; CHECK-P9-LE-NEXT:    neg r5, r3
59; CHECK-P9-LE-NEXT:    addi r3, r31, 48
60; CHECK-P9-LE-NEXT:    divd r7, r5, r6
61; CHECK-P9-LE-NEXT:    add r4, r1, r5
62; CHECK-P9-LE-NEXT:    mulld r6, r7, r6
63; CHECK-P9-LE-NEXT:    sub r5, r5, r6
64; CHECK-P9-LE-NEXT:    stdux r3, r1, r5
65; CHECK-P9-LE-NEXT:    cmpd r1, r4
66; CHECK-P9-LE-NEXT:    beq cr0, .LBB0_2
67; CHECK-P9-LE-NEXT:  .LBB0_1:
68; CHECK-P9-LE-NEXT:    stdu r3, -32768(r1)
69; CHECK-P9-LE-NEXT:    cmpd r1, r4
70; CHECK-P9-LE-NEXT:    bne cr0, .LBB0_1
71; CHECK-P9-LE-NEXT:  .LBB0_2:
72; CHECK-P9-LE-NEXT:    li r4, 1
73; CHECK-P9-LE-NEXT:    addi r3, r1, 32
74; CHECK-P9-LE-NEXT:    stw r4, 4792(r3)
75; CHECK-P9-LE-NEXT:    lwz r3, 0(r3)
76; CHECK-P9-LE-NEXT:    ld r1, 0(r1)
77; CHECK-P9-LE-NEXT:    ld r31, -8(r1)
78; CHECK-P9-LE-NEXT:    blr
79;
80; CHECK-BE-LABEL: foo:
81; CHECK-BE:       # %bb.0:
82; CHECK-BE-NEXT:    std r31, -8(r1)
83; CHECK-BE-NEXT:    stdu r1, -64(r1)
84; CHECK-BE-NEXT:    rldic r3, r3, 2, 30
85; CHECK-BE-NEXT:    li r5, -32768
86; CHECK-BE-NEXT:    addi r3, r3, 15
87; CHECK-BE-NEXT:    rldicl r3, r3, 60, 4
88; CHECK-BE-NEXT:    mr r31, r1
89; CHECK-BE-NEXT:    rldicl r3, r3, 4, 29
90; CHECK-BE-NEXT:    neg r4, r3
91; CHECK-BE-NEXT:    divd r6, r4, r5
92; CHECK-BE-NEXT:    addi r3, r31, 64
93; CHECK-BE-NEXT:    mulld r5, r6, r5
94; CHECK-BE-NEXT:    sub r5, r4, r5
95; CHECK-BE-NEXT:    add r4, r1, r4
96; CHECK-BE-NEXT:    stdux r3, r1, r5
97; CHECK-BE-NEXT:    cmpd r1, r4
98; CHECK-BE-NEXT:    beq cr0, .LBB0_2
99; CHECK-BE-NEXT:  .LBB0_1:
100; CHECK-BE-NEXT:    stdu r3, -32768(r1)
101; CHECK-BE-NEXT:    cmpd r1, r4
102; CHECK-BE-NEXT:    bne cr0, .LBB0_1
103; CHECK-BE-NEXT:  .LBB0_2:
104; CHECK-BE-NEXT:    li r4, 1
105; CHECK-BE-NEXT:    addi r3, r1, 48
106; CHECK-BE-NEXT:    stw r4, 4792(r3)
107; CHECK-BE-NEXT:    lwz r3, 0(r3)
108; CHECK-BE-NEXT:    ld r1, 0(r1)
109; CHECK-BE-NEXT:    ld r31, -8(r1)
110; CHECK-BE-NEXT:    blr
111;
112; CHECK-32-LABEL: foo:
113; CHECK-32:       # %bb.0:
114; CHECK-32-NEXT:    stwu r1, -32(r1)
115; CHECK-32-NEXT:    slwi r3, r3, 2
116; CHECK-32-NEXT:    addi r3, r3, 15
117; CHECK-32-NEXT:    rlwinm r3, r3, 0, 0, 27
118; CHECK-32-NEXT:    neg r4, r3
119; CHECK-32-NEXT:    li r5, -32768
120; CHECK-32-NEXT:    divw r6, r4, r5
121; CHECK-32-NEXT:    stw r31, 28(r1)
122; CHECK-32-NEXT:    mr r31, r1
123; CHECK-32-NEXT:    addi r3, r31, 32
124; CHECK-32-NEXT:    mullw r5, r6, r5
125; CHECK-32-NEXT:    sub r5, r4, r5
126; CHECK-32-NEXT:    add r4, r1, r4
127; CHECK-32-NEXT:    stwux r3, r1, r5
128; CHECK-32-NEXT:    cmpw r1, r4
129; CHECK-32-NEXT:    beq cr0, .LBB0_2
130; CHECK-32-NEXT:  .LBB0_1:
131; CHECK-32-NEXT:    stwu r3, -32768(r1)
132; CHECK-32-NEXT:    cmpw r1, r4
133; CHECK-32-NEXT:    bne cr0, .LBB0_1
134; CHECK-32-NEXT:  .LBB0_2:
135; CHECK-32-NEXT:    li r4, 1
136; CHECK-32-NEXT:    addi r3, r1, 16
137; CHECK-32-NEXT:    stw r4, 4792(r3)
138; CHECK-32-NEXT:    lwz r3, 0(r3)
139; CHECK-32-NEXT:    lwz r31, 0(r1)
140; CHECK-32-NEXT:    lwz r0, -4(r31)
141; CHECK-32-NEXT:    mr r1, r31
142; CHECK-32-NEXT:    mr r31, r0
143; CHECK-32-NEXT:    blr
144  %a = alloca i32, i32 %n, align 16
145  %b = getelementptr inbounds i32, i32* %a, i64 1198
146  store volatile i32 1, i32* %b
147  %c = load volatile i32, i32* %a
148  ret i32 %c
149}
150
151define i32 @bar(i32 %n) local_unnamed_addr #0 nounwind {
152; CHECK-LE-LABEL: bar:
153; CHECK-LE:       # %bb.0:
154; CHECK-LE-NEXT:    std r31, -8(r1)
155; CHECK-LE-NEXT:    stdu r1, -48(r1)
156; CHECK-LE-NEXT:    rldic r4, r3, 2, 30
157; CHECK-LE-NEXT:    li r6, -4096
158; CHECK-LE-NEXT:    mr r31, r1
159; CHECK-LE-NEXT:    addi r4, r4, 15
160; CHECK-LE-NEXT:    rldicl r4, r4, 60, 4
161; CHECK-LE-NEXT:    rldicl r4, r4, 4, 29
162; CHECK-LE-NEXT:    neg r5, r4
163; CHECK-LE-NEXT:    addi r4, r31, 48
164; CHECK-LE-NEXT:    divd r7, r5, r6
165; CHECK-LE-NEXT:    mulld r6, r7, r6
166; CHECK-LE-NEXT:    sub r6, r5, r6
167; CHECK-LE-NEXT:    add r5, r1, r5
168; CHECK-LE-NEXT:    stdux r4, r1, r6
169; CHECK-LE-NEXT:    cmpd r1, r5
170; CHECK-LE-NEXT:    beq cr0, .LBB1_2
171; CHECK-LE-NEXT:  .LBB1_1:
172; CHECK-LE-NEXT:    stdu r4, -4096(r1)
173; CHECK-LE-NEXT:    cmpd r1, r5
174; CHECK-LE-NEXT:    bne cr0, .LBB1_1
175; CHECK-LE-NEXT:  .LBB1_2:
176; CHECK-LE-NEXT:    extsw r3, r3
177; CHECK-LE-NEXT:    li r5, 1
178; CHECK-LE-NEXT:    addi r4, r1, 32
179; CHECK-LE-NEXT:    sldi r3, r3, 2
180; CHECK-LE-NEXT:    add r3, r4, r3
181; CHECK-LE-NEXT:    stw r5, 4096(r3)
182; CHECK-LE-NEXT:    lwz r3, 0(r4)
183; CHECK-LE-NEXT:    ld r1, 0(r1)
184; CHECK-LE-NEXT:    ld r31, -8(r1)
185; CHECK-LE-NEXT:    blr
186;
187; CHECK-P9-LE-LABEL: bar:
188; CHECK-P9-LE:       # %bb.0:
189; CHECK-P9-LE-NEXT:    std r31, -8(r1)
190; CHECK-P9-LE-NEXT:    stdu r1, -48(r1)
191; CHECK-P9-LE-NEXT:    rldic r4, r3, 2, 30
192; CHECK-P9-LE-NEXT:    addi r4, r4, 15
193; CHECK-P9-LE-NEXT:    li r7, -4096
194; CHECK-P9-LE-NEXT:    mr r31, r1
195; CHECK-P9-LE-NEXT:    rldicl r4, r4, 60, 4
196; CHECK-P9-LE-NEXT:    rldicl r4, r4, 4, 29
197; CHECK-P9-LE-NEXT:    neg r6, r4
198; CHECK-P9-LE-NEXT:    addi r4, r31, 48
199; CHECK-P9-LE-NEXT:    divd r8, r6, r7
200; CHECK-P9-LE-NEXT:    add r5, r1, r6
201; CHECK-P9-LE-NEXT:    mulld r7, r8, r7
202; CHECK-P9-LE-NEXT:    sub r6, r6, r7
203; CHECK-P9-LE-NEXT:    stdux r4, r1, r6
204; CHECK-P9-LE-NEXT:    cmpd r1, r5
205; CHECK-P9-LE-NEXT:    beq cr0, .LBB1_2
206; CHECK-P9-LE-NEXT:  .LBB1_1:
207; CHECK-P9-LE-NEXT:    stdu r4, -4096(r1)
208; CHECK-P9-LE-NEXT:    cmpd r1, r5
209; CHECK-P9-LE-NEXT:    bne cr0, .LBB1_1
210; CHECK-P9-LE-NEXT:  .LBB1_2:
211; CHECK-P9-LE-NEXT:    extswsli r3, r3, 2
212; CHECK-P9-LE-NEXT:    li r5, 1
213; CHECK-P9-LE-NEXT:    addi r4, r1, 32
214; CHECK-P9-LE-NEXT:    add r3, r4, r3
215; CHECK-P9-LE-NEXT:    stw r5, 4096(r3)
216; CHECK-P9-LE-NEXT:    lwz r3, 0(r4)
217; CHECK-P9-LE-NEXT:    ld r1, 0(r1)
218; CHECK-P9-LE-NEXT:    ld r31, -8(r1)
219; CHECK-P9-LE-NEXT:    blr
220;
221; CHECK-BE-LABEL: bar:
222; CHECK-BE:       # %bb.0:
223; CHECK-BE-NEXT:    std r31, -8(r1)
224; CHECK-BE-NEXT:    stdu r1, -64(r1)
225; CHECK-BE-NEXT:    rldic r4, r3, 2, 30
226; CHECK-BE-NEXT:    li r6, -4096
227; CHECK-BE-NEXT:    addi r4, r4, 15
228; CHECK-BE-NEXT:    rldicl r4, r4, 60, 4
229; CHECK-BE-NEXT:    mr r31, r1
230; CHECK-BE-NEXT:    rldicl r4, r4, 4, 29
231; CHECK-BE-NEXT:    neg r5, r4
232; CHECK-BE-NEXT:    divd r7, r5, r6
233; CHECK-BE-NEXT:    addi r4, r31, 64
234; CHECK-BE-NEXT:    mulld r6, r7, r6
235; CHECK-BE-NEXT:    sub r6, r5, r6
236; CHECK-BE-NEXT:    add r5, r1, r5
237; CHECK-BE-NEXT:    stdux r4, r1, r6
238; CHECK-BE-NEXT:    cmpd r1, r5
239; CHECK-BE-NEXT:    beq cr0, .LBB1_2
240; CHECK-BE-NEXT:  .LBB1_1:
241; CHECK-BE-NEXT:    stdu r4, -4096(r1)
242; CHECK-BE-NEXT:    cmpd r1, r5
243; CHECK-BE-NEXT:    bne cr0, .LBB1_1
244; CHECK-BE-NEXT:  .LBB1_2:
245; CHECK-BE-NEXT:    extsw r3, r3
246; CHECK-BE-NEXT:    addi r4, r1, 48
247; CHECK-BE-NEXT:    sldi r3, r3, 2
248; CHECK-BE-NEXT:    li r5, 1
249; CHECK-BE-NEXT:    add r3, r4, r3
250; CHECK-BE-NEXT:    stw r5, 4096(r3)
251; CHECK-BE-NEXT:    lwz r3, 0(r4)
252; CHECK-BE-NEXT:    ld r1, 0(r1)
253; CHECK-BE-NEXT:    ld r31, -8(r1)
254; CHECK-BE-NEXT:    blr
255;
256; CHECK-32-LABEL: bar:
257; CHECK-32:       # %bb.0:
258; CHECK-32-NEXT:    stwu r1, -32(r1)
259; CHECK-32-NEXT:    slwi r3, r3, 2
260; CHECK-32-NEXT:    addi r4, r3, 15
261; CHECK-32-NEXT:    rlwinm r4, r4, 0, 0, 27
262; CHECK-32-NEXT:    neg r5, r4
263; CHECK-32-NEXT:    li r6, -4096
264; CHECK-32-NEXT:    divw r7, r5, r6
265; CHECK-32-NEXT:    stw r31, 28(r1)
266; CHECK-32-NEXT:    mr r31, r1
267; CHECK-32-NEXT:    addi r4, r31, 32
268; CHECK-32-NEXT:    mullw r6, r7, r6
269; CHECK-32-NEXT:    sub r6, r5, r6
270; CHECK-32-NEXT:    add r5, r1, r5
271; CHECK-32-NEXT:    stwux r4, r1, r6
272; CHECK-32-NEXT:    cmpw r1, r5
273; CHECK-32-NEXT:    beq cr0, .LBB1_2
274; CHECK-32-NEXT:  .LBB1_1:
275; CHECK-32-NEXT:    stwu r4, -4096(r1)
276; CHECK-32-NEXT:    cmpw r1, r5
277; CHECK-32-NEXT:    bne cr0, .LBB1_1
278; CHECK-32-NEXT:  .LBB1_2:
279; CHECK-32-NEXT:    addi r4, r1, 16
280; CHECK-32-NEXT:    li r5, 1
281; CHECK-32-NEXT:    add r3, r4, r3
282; CHECK-32-NEXT:    stw r5, 4096(r3)
283; CHECK-32-NEXT:    lwz r3, 0(r4)
284; CHECK-32-NEXT:    lwz r31, 0(r1)
285; CHECK-32-NEXT:    lwz r0, -4(r31)
286; CHECK-32-NEXT:    mr r1, r31
287; CHECK-32-NEXT:    mr r31, r0
288; CHECK-32-NEXT:    blr
289  %a = alloca i32, i32 %n, align 16
290  %i = add i32 %n, 1024
291  %b = getelementptr inbounds i32, i32* %a, i32 %i
292  store volatile i32 1, i32* %b
293  %c = load volatile i32, i32* %a
294  ret i32 %c
295}
296
297define i32 @f(i32 %n) local_unnamed_addr #0 "stack-probe-size"="65536" nounwind {
298; CHECK-LE-LABEL: f:
299; CHECK-LE:       # %bb.0:
300; CHECK-LE-NEXT:    std r31, -8(r1)
301; CHECK-LE-NEXT:    stdu r1, -48(r1)
302; CHECK-LE-NEXT:    rldic r3, r3, 2, 30
303; CHECK-LE-NEXT:    lis r4, -1
304; CHECK-LE-NEXT:    mr r31, r1
305; CHECK-LE-NEXT:    addi r3, r3, 15
306; CHECK-LE-NEXT:    ori r4, r4, 0
307; CHECK-LE-NEXT:    rldicl r3, r3, 60, 4
308; CHECK-LE-NEXT:    rldicl r3, r3, 4, 29
309; CHECK-LE-NEXT:    neg r5, r3
310; CHECK-LE-NEXT:    addi r3, r31, 48
311; CHECK-LE-NEXT:    divd r6, r5, r4
312; CHECK-LE-NEXT:    mulld r6, r6, r4
313; CHECK-LE-NEXT:    sub r6, r5, r6
314; CHECK-LE-NEXT:    add r5, r1, r5
315; CHECK-LE-NEXT:    stdux r3, r1, r6
316; CHECK-LE-NEXT:    cmpd r1, r5
317; CHECK-LE-NEXT:    beq cr0, .LBB2_2
318; CHECK-LE-NEXT:  .LBB2_1:
319; CHECK-LE-NEXT:    stdux r3, r1, r4
320; CHECK-LE-NEXT:    cmpd r1, r5
321; CHECK-LE-NEXT:    bne cr0, .LBB2_1
322; CHECK-LE-NEXT:  .LBB2_2:
323; CHECK-LE-NEXT:    li r4, 1
324; CHECK-LE-NEXT:    addi r3, r1, 32
325; CHECK-LE-NEXT:    stw r4, 4792(r3)
326; CHECK-LE-NEXT:    lwz r3, 0(r3)
327; CHECK-LE-NEXT:    ld r1, 0(r1)
328; CHECK-LE-NEXT:    ld r31, -8(r1)
329; CHECK-LE-NEXT:    blr
330;
331; CHECK-P9-LE-LABEL: f:
332; CHECK-P9-LE:       # %bb.0:
333; CHECK-P9-LE-NEXT:    std r31, -8(r1)
334; CHECK-P9-LE-NEXT:    stdu r1, -48(r1)
335; CHECK-P9-LE-NEXT:    rldic r3, r3, 2, 30
336; CHECK-P9-LE-NEXT:    addi r3, r3, 15
337; CHECK-P9-LE-NEXT:    lis r5, -1
338; CHECK-P9-LE-NEXT:    ori r5, r5, 0
339; CHECK-P9-LE-NEXT:    mr r31, r1
340; CHECK-P9-LE-NEXT:    rldicl r3, r3, 60, 4
341; CHECK-P9-LE-NEXT:    rldicl r3, r3, 4, 29
342; CHECK-P9-LE-NEXT:    neg r6, r3
343; CHECK-P9-LE-NEXT:    addi r3, r31, 48
344; CHECK-P9-LE-NEXT:    divd r7, r6, r5
345; CHECK-P9-LE-NEXT:    add r4, r1, r6
346; CHECK-P9-LE-NEXT:    mulld r7, r7, r5
347; CHECK-P9-LE-NEXT:    sub r6, r6, r7
348; CHECK-P9-LE-NEXT:    stdux r3, r1, r6
349; CHECK-P9-LE-NEXT:    cmpd r1, r4
350; CHECK-P9-LE-NEXT:    beq cr0, .LBB2_2
351; CHECK-P9-LE-NEXT:  .LBB2_1:
352; CHECK-P9-LE-NEXT:    stdux r3, r1, r5
353; CHECK-P9-LE-NEXT:    cmpd r1, r4
354; CHECK-P9-LE-NEXT:    bne cr0, .LBB2_1
355; CHECK-P9-LE-NEXT:  .LBB2_2:
356; CHECK-P9-LE-NEXT:    li r4, 1
357; CHECK-P9-LE-NEXT:    addi r3, r1, 32
358; CHECK-P9-LE-NEXT:    stw r4, 4792(r3)
359; CHECK-P9-LE-NEXT:    lwz r3, 0(r3)
360; CHECK-P9-LE-NEXT:    ld r1, 0(r1)
361; CHECK-P9-LE-NEXT:    ld r31, -8(r1)
362; CHECK-P9-LE-NEXT:    blr
363;
364; CHECK-BE-LABEL: f:
365; CHECK-BE:       # %bb.0:
366; CHECK-BE-NEXT:    std r31, -8(r1)
367; CHECK-BE-NEXT:    stdu r1, -64(r1)
368; CHECK-BE-NEXT:    rldic r3, r3, 2, 30
369; CHECK-BE-NEXT:    lis r4, -1
370; CHECK-BE-NEXT:    addi r3, r3, 15
371; CHECK-BE-NEXT:    rldicl r3, r3, 60, 4
372; CHECK-BE-NEXT:    ori r4, r4, 0
373; CHECK-BE-NEXT:    rldicl r3, r3, 4, 29
374; CHECK-BE-NEXT:    mr r31, r1
375; CHECK-BE-NEXT:    neg r5, r3
376; CHECK-BE-NEXT:    divd r6, r5, r4
377; CHECK-BE-NEXT:    addi r3, r31, 64
378; CHECK-BE-NEXT:    mulld r6, r6, r4
379; CHECK-BE-NEXT:    sub r6, r5, r6
380; CHECK-BE-NEXT:    add r5, r1, r5
381; CHECK-BE-NEXT:    stdux r3, r1, r6
382; CHECK-BE-NEXT:    cmpd r1, r5
383; CHECK-BE-NEXT:    beq cr0, .LBB2_2
384; CHECK-BE-NEXT:  .LBB2_1:
385; CHECK-BE-NEXT:    stdux r3, r1, r4
386; CHECK-BE-NEXT:    cmpd r1, r5
387; CHECK-BE-NEXT:    bne cr0, .LBB2_1
388; CHECK-BE-NEXT:  .LBB2_2:
389; CHECK-BE-NEXT:    li r4, 1
390; CHECK-BE-NEXT:    addi r3, r1, 48
391; CHECK-BE-NEXT:    stw r4, 4792(r3)
392; CHECK-BE-NEXT:    lwz r3, 0(r3)
393; CHECK-BE-NEXT:    ld r1, 0(r1)
394; CHECK-BE-NEXT:    ld r31, -8(r1)
395; CHECK-BE-NEXT:    blr
396;
397; CHECK-32-LABEL: f:
398; CHECK-32:       # %bb.0:
399; CHECK-32-NEXT:    stwu r1, -32(r1)
400; CHECK-32-NEXT:    slwi r3, r3, 2
401; CHECK-32-NEXT:    addi r3, r3, 15
402; CHECK-32-NEXT:    rlwinm r3, r3, 0, 0, 27
403; CHECK-32-NEXT:    lis r4, -1
404; CHECK-32-NEXT:    neg r5, r3
405; CHECK-32-NEXT:    ori r4, r4, 0
406; CHECK-32-NEXT:    divw r6, r5, r4
407; CHECK-32-NEXT:    stw r31, 28(r1)
408; CHECK-32-NEXT:    mr r31, r1
409; CHECK-32-NEXT:    addi r3, r31, 32
410; CHECK-32-NEXT:    mullw r6, r6, r4
411; CHECK-32-NEXT:    sub r6, r5, r6
412; CHECK-32-NEXT:    add r5, r1, r5
413; CHECK-32-NEXT:    stwux r3, r1, r6
414; CHECK-32-NEXT:    cmpw r1, r5
415; CHECK-32-NEXT:    beq cr0, .LBB2_2
416; CHECK-32-NEXT:  .LBB2_1:
417; CHECK-32-NEXT:    stwux r3, r1, r4
418; CHECK-32-NEXT:    cmpw r1, r5
419; CHECK-32-NEXT:    bne cr0, .LBB2_1
420; CHECK-32-NEXT:  .LBB2_2:
421; CHECK-32-NEXT:    li r4, 1
422; CHECK-32-NEXT:    addi r3, r1, 16
423; CHECK-32-NEXT:    stw r4, 4792(r3)
424; CHECK-32-NEXT:    lwz r3, 0(r3)
425; CHECK-32-NEXT:    lwz r31, 0(r1)
426; CHECK-32-NEXT:    lwz r0, -4(r31)
427; CHECK-32-NEXT:    mr r1, r31
428; CHECK-32-NEXT:    mr r31, r0
429; CHECK-32-NEXT:    blr
430  %a = alloca i32, i32 %n, align 16
431  %b = getelementptr inbounds i32, i32* %a, i64 1198
432  store volatile i32 1, i32* %b
433  %c = load volatile i32, i32* %a
434  ret i32 %c
435}
436
437attributes #0 =  {"probe-stack"="inline-asm"}
438