1; Check the miscellaneous logical vector operations added in P8
2;
3; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s
4; Test x eqv y
5define <4 x i32> @test_veqv(<4 x i32> %x, <4 x i32> %y) nounwind {
6       %tmp = xor <4 x i32> %x, %y
7       %ret_val = xor <4 x i32> %tmp, < i32 -1, i32 -1, i32 -1, i32 -1>
8       ret <4 x i32> %ret_val
9; CHECK: veqv 2, 2, 3
10}
11
12; Test x vnand y
13define <4 x i32> @test_vnand(<4 x i32> %x, <4 x i32> %y) nounwind {
14       %tmp = and <4 x i32> %x, %y
15       %ret_val = xor <4 x i32> %tmp, <i32 -1, i32 -1, i32 -1, i32 -1>
16       ret <4 x i32> %ret_val
17; CHECK: vnand 2, 2, 3
18}
19
20; Test x vorc y and variants
21define <4 x i32> @test_vorc(<4 x i32> %x, <4 x i32> %y) nounwind {
22       %tmp1 = xor <4 x i32> %y, <i32 -1, i32 -1, i32 -1, i32 -1>
23       %tmp2 = or <4 x i32> %x, %tmp1
24; CHECK: vorc 3, 2, 3
25       %tmp3 = xor <4 x i32> %tmp2, <i32 -1, i32 -1, i32 -1, i32 -1>
26       %tmp4 = or <4 x i32> %tmp3, %x
27; CHECK: vorc 2, 2, 3
28       ret <4 x i32> %tmp4
29}
30