1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
3; RUN:   | FileCheck -check-prefix=RV32I %s
4
5; Ensure that the ISDOpcodes ADDC, ADDE, SUBC, SUBE are handled correctly
6
7define i64 @addc_adde(i64 %a, i64 %b) nounwind {
8; RV32I-LABEL: addc_adde:
9; RV32I:       # %bb.0:
10; RV32I-NEXT:    add a1, a1, a3
11; RV32I-NEXT:    add a2, a0, a2
12; RV32I-NEXT:    sltu a0, a2, a0
13; RV32I-NEXT:    add a1, a1, a0
14; RV32I-NEXT:    mv a0, a2
15; RV32I-NEXT:    ret
16  %1 = add i64 %a, %b
17  ret i64 %1
18}
19
20define i64 @subc_sube(i64 %a, i64 %b) nounwind {
21; RV32I-LABEL: subc_sube:
22; RV32I:       # %bb.0:
23; RV32I-NEXT:    sltu a4, a0, a2
24; RV32I-NEXT:    sub a1, a1, a3
25; RV32I-NEXT:    sub a1, a1, a4
26; RV32I-NEXT:    sub a0, a0, a2
27; RV32I-NEXT:    ret
28  %1 = sub i64 %a, %b
29  ret i64 %1
30}
31