1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
3; RUN:   | FileCheck -check-prefix=RV32I %s
4
5declare {i32, i1} @llvm.sadd.with.overflow.i32(i32 %a, i32 %b)
6declare {i32, i1} @llvm.ssub.with.overflow.i32(i32 %a, i32 %b)
7declare {i32, i1} @llvm.uadd.with.overflow.i32(i32 %a, i32 %b)
8declare {i32, i1} @llvm.usub.with.overflow.i32(i32 %a, i32 %b)
9
10define i1 @sadd(i32 %a, i32 %b, i32* %c) nounwind {
11; RV32I-LABEL: sadd:
12; RV32I:       # %bb.0: # %entry
13; RV32I-NEXT:    add a3, a0, a1
14; RV32I-NEXT:    slt a0, a3, a0
15; RV32I-NEXT:    slti a1, a1, 0
16; RV32I-NEXT:    xor a0, a1, a0
17; RV32I-NEXT:    sw a3, 0(a2)
18; RV32I-NEXT:    ret
19entry:
20  %x = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %a, i32 %b)
21  %calc = extractvalue {i32, i1} %x, 0
22  %ovf = extractvalue {i32, i1} %x, 1
23  store i32 %calc, i32* %c
24  ret i1 %ovf
25}
26
27define i1 @ssub(i32 %a, i32 %b, i32* %c) nounwind {
28; RV32I-LABEL: ssub:
29; RV32I:       # %bb.0: # %entry
30; RV32I-NEXT:    sgtz a3, a1
31; RV32I-NEXT:    sub a1, a0, a1
32; RV32I-NEXT:    slt a0, a1, a0
33; RV32I-NEXT:    xor a0, a3, a0
34; RV32I-NEXT:    sw a1, 0(a2)
35; RV32I-NEXT:    ret
36entry:
37  %x = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %a, i32 %b)
38  %calc = extractvalue {i32, i1} %x, 0
39  %ovf = extractvalue {i32, i1} %x, 1
40  store i32 %calc, i32* %c
41  ret i1 %ovf
42}
43
44define i1 @uadd(i32 %a, i32 %b, i32* %c) nounwind {
45; RV32I-LABEL: uadd:
46; RV32I:       # %bb.0: # %entry
47; RV32I-NEXT:    add a1, a0, a1
48; RV32I-NEXT:    sltu a0, a1, a0
49; RV32I-NEXT:    sw a1, 0(a2)
50; RV32I-NEXT:    ret
51entry:
52  %x = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %a, i32 %b)
53  %calc = extractvalue {i32, i1} %x, 0
54  %ovf = extractvalue {i32, i1} %x, 1
55  store i32 %calc, i32* %c
56  ret i1 %ovf
57}
58
59define i1 @usub(i32 %a, i32 %b, i32* %c) nounwind {
60; RV32I-LABEL: usub:
61; RV32I:       # %bb.0: # %entry
62; RV32I-NEXT:    sub a1, a0, a1
63; RV32I-NEXT:    sltu a0, a0, a1
64; RV32I-NEXT:    sw a1, 0(a2)
65; RV32I-NEXT:    ret
66entry:
67  %x = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %a, i32 %b)
68  %calc = extractvalue {i32, i1} %x, 0
69  %ovf = extractvalue {i32, i1} %x, 1
70  store i32 %calc, i32* %c
71  ret i1 %ovf
72}
73