1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
3; RUN:   | FileCheck %s -check-prefix=RV32I
4
5define i32 @bare_select(i1 %a, i32 %b, i32 %c) nounwind {
6; RV32I-LABEL: bare_select:
7; RV32I:       # %bb.0:
8; RV32I-NEXT:    andi a3, a0, 1
9; RV32I-NEXT:    mv a0, a1
10; RV32I-NEXT:    bnez a3, .LBB0_2
11; RV32I-NEXT:  # %bb.1:
12; RV32I-NEXT:    mv a0, a2
13; RV32I-NEXT:  .LBB0_2:
14; RV32I-NEXT:    ret
15  %1 = select i1 %a, i32 %b, i32 %c
16  ret i32 %1
17}
18
19define float @bare_select_float(i1 %a, float %b, float %c) nounwind {
20; RV32I-LABEL: bare_select_float:
21; RV32I:       # %bb.0:
22; RV32I-NEXT:    andi a3, a0, 1
23; RV32I-NEXT:    mv a0, a1
24; RV32I-NEXT:    bnez a3, .LBB1_2
25; RV32I-NEXT:  # %bb.1:
26; RV32I-NEXT:    mv a0, a2
27; RV32I-NEXT:  .LBB1_2:
28; RV32I-NEXT:    ret
29  %1 = select i1 %a, float %b, float %c
30  ret float %1
31}
32